Memory-efficient on-chip network with adaptive interfaces

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 1, 2012, Pages 146-159

  Daneshtalab, Masoud ^a   Ebrahimi, Masoumeh ^a   Liljeberg, Pasi ^a   Plosila, Juha ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

AXI transaction protocol; memory controller; network interface; networks on chip

Indexed keywords

ADAPTIVE INTERFACE; CRITICAL ISSUES; DYNAMIC RANDOM ACCESS MEMORY; INTELLECTUAL PROPERTY CORES; MEMORY ACCESS; MEMORY ACCESS LATENCY; MEMORY BANDWIDTHS; MEMORY CONTROLLER; MEMORY LATENCIES; MEMORY UTILIZATION; MULTI PROCESSOR ARCHITECTURE; NETWORK INTERFACE; NETWORK LATENCIES; NETWORK-BASED; NETWORKS ON CHIPS; ON-CHIP NETWORKS; OUT OF ORDER; PRIORITY-BASED; RESOURCE UTILIZATIONS; SYNTHETIC TESTS; TRANSACTION PROTOCOL;

DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE;

NETWORK ARCHITECTURE;

EID: 84255204493     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2160348     Document Type: Article

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