A low-latency and memory-efficient on-chip network

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 99-106

  Daneshtalab, Masoud ^a   Ebrahimi, Masoumeh ^a   Liljeberg, Pasi ^a   Plosila, Juha ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL ISSUES; IP CORE; LOW-LATENCY; MEMORY ACCESS LATENCY; MEMORY CONTROLLER; MEMORY UTILIZATION; NETWORK INTERFACE; NETWORK INTERFACE ARCHITECTURE; NETWORK LATENCIES; ON-CHIP NETWORKS; PROPOSED ARCHITECTURES; RESOURCE UTILIZATIONS; SYNTHETIC TESTS;

INTERNET PROTOCOLS; MICROPROCESSOR CHIPS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 77955098839     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.19     Document Type: Conference Paper

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