A generic network interface architecture for a Networked Processor Array (NePA)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4934 LNCS, Issue , 2008, Pages 247-260

  Lee, Seung Eun ^a   Bahn, Jun Ho ^a   Yang, Yoon Seok ^a   Bagherzadeh, Nader ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Interconnection network; Multiprocessor System on Chip (MPSoC); Network interface; Network on Chip (NoC); Networked Processor Array (NePA)

Indexed keywords

COMPUTER SYSTEMS; DECODING; INTERCONNECTION NETWORKS; TELECOMMUNICATION NETWORKS;

CASE STUDIES; COMPUTING SYSTEMS; DESIGN CYCLES; GENERIC ARCHITECTURES; INTERCONNECTION NETWORK; INTERFACE SPECIFICATIONS; INTERNATIONAL CONFERENCES; MULTI-PROCESSOR SOC; MULTIPROCESSOR SYSTEM-ON-CHIP (MPSOC); NETWORK INTERFACE; NETWORK INTERFACE ARCHITECTURE; NETWORK INTERFACES; NETWORK-ON-CHIP; NETWORK-ON-CHIP (NOC); NETWORKED PROCESSOR ARRAY (NEPA); ON-CHIP INTERCONNECTION NETWORKS; PROCESSOR ARRAYS; SYSTEMATIC DESIGNS; TURBO DECODERS;

ELECTRIC NETWORK TOPOLOGY;

EID: 49949110568     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-78153-0_19     Document Type: Conference Paper

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