Reliability aware NoC router architecture using input channel buffer sharing

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2009, Pages 511-516

  Neishaburi, M H ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

Network on chip; System on chip; Virtual channel

Indexed keywords

BUFFER SHARING; INPUT CHANNELS; INPUT PORT; MICRO ARCHITECTURES; NETWORK BANDWIDTH; NETWORK ON CHIP; ON-CHIP NETWORKS; PACKET LATENCIES; ROUTER ARCHITECTURE; SYSTEM ON CHIP; TRAFFIC PATTERN; VIRTUAL CHANNEL; VIRTUAL CHANNELS;

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; DATA COMPRESSION; DISTRIBUTED COMPUTER SYSTEMS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; LAKES; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; RELIABILITY;

ROUTERS;

EID: 70350615933     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531542.1531658     Document Type: Conference Paper

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