Core-aware memory access scheduling schemes

IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium

Volumn , Issue , 2009, Pages

  Fang, Zhibin ^a   Sun, Xian He ^a   Chen, Yong ^a   Byna, Surendra ^a  

^a Illinois Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EXECUTION TIME; HARDWARE STRUCTURES; MEMORY ACCESS; MEMORY SCHEDULING; MULTI CORE; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; NAS PARALLEL BENCHMARKS; RESOURCE MANAGEMENT; SIMULATION RESULT; SYSTEM SCHEDULING;

DISTRIBUTED PARAMETER NETWORKS; MICROPROCESSOR CHIPS; RESOURCE ALLOCATION;

SCHEDULING;

EID: 70450080068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2009.5161013     Document Type: Conference Paper

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