Simplified 20-μm pitch vertical interconnection process for 3D chip stacking

IEEJ Transactions on Electrical and Electronic Engineering

Volumn 4, Issue 3, 2009, Pages 339-344

  Sakuma, Katsuyuki ^a,b   Nagai, Noriyasu ^a   Saito, Mikiko ^a   Mizuno, Jun ^a   Shoji, Shuichi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b IBM RESEARCH TOKYO   (Japan)

Author keywords

3D integration; Electroplating; Lead free solder; Microbump; Through silicon via (TSV)

Indexed keywords

ASPECT RATIO; BRAZING; CONDUCTIVE MATERIALS; ELECTRONICS PACKAGING; ELECTROPLATING; LEAD; TIN; WELDING;

3D INTEGRATION; CHIP STACKING; CU ELECTROPLATING; FILLING MATERIALS; HIGH ASPECT RATIO; LEAD-FREE SOLDER; MICRO-BUMPS; MICROBUMP; NEW PROCESS; NI ELECTROPLATING; PROCESSING STAGE; PROTOTYPE CHIP; THREE-DIMENSIONAL (3D); THROUGH SILICON VIAS; THROUGH-SILICON-VIA (TSV); UNIQUE FEATURES; VERTICAL INTERCONNECTIONS;

THREE DIMENSIONAL;

EID: 67649255123     PISSN: 19314973     EISSN: 19314981     Source Type: Journal    
DOI: 10.1002/tee.20415     Document Type: Article

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