Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 58, Issue 9, 2011, Pages 2051-2060

  Waheed, Khurram ^a   Staszewski, Robert Bogdan ^b   Dülger, Fikret ^c   Ullah, Mahbuba S ^d   Vamvakos, Socrates D ^e  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c Zoran   (United States)

^d UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^e MoSys Inc ^*  (United States)

Author keywords

All digital PLL; deadband; digital to time converter (DTC); dithering; limit cycles; phase error; Phase locked loop; quantization; short dither sequence; time to digital converter (TDC)

Indexed keywords

FREQUENCY CONVERTERS; NANOTECHNOLOGY; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; QUANTIZATION (SIGNAL); SIGNAL DETECTION;

ALL-DIGITAL PLL; DEADBANDS; DIGITAL-TO-TIME CONVERTER (DTC); DITHERING; LIMIT-CYCLE; PHASE ERROR; QUANTIZATION; SHORT DITHER SEQUENCE; TIME TO DIGITAL CONVERTERS;

PHASE COMPARATORS;

EID: 80052885779     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2011.2163981     Document Type: Article

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