Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 7, 2010, Pages 1538-1548

  Maeda, Tadashi ^a   Tokairin, Takashi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

Digitally controlled oscillator; Fourier series expansion; frequency synthesizer; Gaussian distribution; phase noise; quantization noise; sinusoidal analysis; time to digital converter

Indexed keywords

ELECTRIC INVERTERS; FOURIER SERIES; FREQUENCY CONVERTERS; FREQUENCY SYNTHESIZERS; GAUSSIAN DISTRIBUTION; PHASE NOISE; SIGNAL PROCESSING; THRESHOLD VOLTAGE; TIME SERIES ANALYSIS;

DIGITALLY CONTROLLED OSCILLATORS; FOURIER-SERIES EXPANSION; QUANTIZATION NOISE; SINUSOIDAL ANALYSIS; TIME TO DIGITAL CONVERTERS;

GAUSSIAN NOISE (ELECTRONIC);

EID: 77954862644     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2035411     Document Type: Article

References (24)

1. R. B. Staszewski et al., "All-digital TX frequency synthesizer and discrete- time receiver for bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2278-2291, Dec. 2004.
2. M. Lee and A. A. Abidi, "A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution," in Symp. VLSI Circuits Dig. Tech. Papers, 2008, pp. 112-113.
3. C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, "A 3 GHz fractional- N all digital PLL with precise time-to-digital converter calibration and mismatch correction," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 344-345, paper 19.3.
4. C. Hsu, M. Z. Straayer, and H. Perrott, "A low-noise, wide-BW 3.6 GHz digital σδ fractional frequency synthesizer with a noise shaping time-to-digital converter and quantization noise cancellation," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 340-341, paper 19.1.
5. A. S. Yousif and J. W. Haslett, "A fine resolution TDC architecture for next generation PET imaging," IEEE Trans. Nucl. Sci., vol.54, pp. 1574-1582, 2007.
6. V. Ramakrishnan and P. T. Balsara, "A wide-range, high-resolution, compact,CMOStime to digital converter," in Proc. 19th Int. Conf. VLSI Design, 2006, pp. 197-202.
7. J. Tangudu et al., "Quantization noise improvement of time to digital converter (TDC) for ADPLL," in Proc. IEEE ISCAS, 2009, pp. 1020-1023.
8. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a vernier delay line," IEEE J. Solid-State Circuits, vol.35, no.2, pp. 240-247, Feb. 2000.
9. C.-K. Liu, "Analytic nonlinear model for harmonics analysis in CMOS inverters," IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol.45, no.7, pp. 741-745, Jul. 1998.
10. G. Chen and E. G. Friedman, "A Fourier series-based RLC interconnect model for periodic signals," in Proc. IEEE ISCAS, 2005, vol.4, pp. 4126-4129.
11. R. B. Staszewski, D. Leipold, C. M. Hung, and P. T. Balsara, "TDCbased frequency synthesizer for wireless applications," in IEEE RFIC Symp. Dig. Papers, 2004, pp. 215-218, M02D-3.
12. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol.25, no.2, pp. 584-594, Feb. 1990.
13. A. Sripad and D. L. Snyder, "A necessary and sufficient condition for quantization errors to be uniform and white," IEEE Trans. Acoust., Speech, Signal Process., vol.25, no.5, pp. 442-448, 1977.
14. J. P. Jansson, A. Mantyniemi, and J. Kostamovaara, "A CMOS time-todigital converter with better than 10 ps single-shot precision," IEEE J. Solid-State Circuits, vol.41, no.6, pp. 1286-1296, Jun. 2006.
15. T. Hashimoto, H. Yamazaki, A. Muramatsu, T. Sato, and A. Inoue, "Time-to-digital converter with vernier delay mismatch compensation for high resolution on-die clock jitter measurement," in Symp. VLSI Circuits Dig. Tech. Papers, 2008, pp. 166-167.
16. T. E. Rahkonen and J. T. Kostamovaara, "The use of stabilized CMOS delay lines for the digitization of short time intervals," IEEE J. Solid- State Circuits, vol.28, no.8, pp. 887-894, Aug. 1993.
17. E. N. Nikolic, V. G. Oklobdzija, V. Stajonovic, W. Jia, J. K. Chiu, and M. M. Leung, "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol.35, no.6, pp. 876-884, Jun. 2000.
18. R. B. Staszewski, S. Vemulapalli, P. Vallur, J.Wallberg, and P. T. Balsara, "Time-to-digital converter for RF frequency synthesis in 90 nm CMOS," in IEEE RFIC Symp. Dig. Papers, 2005, pp. 473-476.
19. R. B. Staszewski, D. Leipold, C. Hung, and P. T. Balsara, "TDC-Based frequency synthesizer for wireless applications," in IEEE RFIC Symp. Dig. Papers, 2005, pp. 215-218.
20. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 2000, pp. 319-321.
21. B.Wicht, T. Nirschl, and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE J. Solid-State Circuits, vol.39, no.7, pp. 1148-1158, Jul. 2004.
22. R. B. Staszewski, S. Vemulapalli, P. Vallur, J.Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II: Express Briefs, vol.53, no.3, pp. 220-224, Mar. 2006.
23. V. Kratyuk, P. K. Hanumolu, K. Ok, U. K. Moon, and K. Mayaram, "A digital PLL with a stochastic time-to-digital converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.56, no.8, pp. 1612-1621, Aug. 2009.
24. J. Jansson, A. Mantyniemi, and J. Kostamovaara, "Synchronization in a multilevel CMOS time-to-digital converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.56, no.8, pp. 1622-1634, Aug. 2009.