A 12-Bit vernier ring time-to-digital converter in 0.13 μ CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 830-842

  Yu, Jianjun ^a   Dai, Fa Foster ^a   Jaeger, Richard C ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

Digital phase locked loop (DPLL); Frequency synthesis; Time and phase measurement; Time to digital converter (TDC); Vernier

Indexed keywords

CLOCK FREQUENCY; CMOS TECHNOLOGY; CORE AREA; DELAY CELL; DIE SIZE; DIGITAL PHASE LOCKED LOOPS; FREQUENCY SYNTHESIS; LOGIC UNIT; LOW-POWER CONSUMPTION; NEGATIVE PHASE; POWER SUPPLY; TIME INTERVAL; TIME RESOLUTION; TIME TO DIGITAL CONVERTERS; TOTAL POWER CONSUMPTION;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; PHASE LOCKED LOOPS;

PHASE MEASUREMENT;

EID: 77950272492     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2040306     Document Type: Conference Paper

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