Noise analysis of time-to-digital converter in all-digital PLLs

2006 IEEE Dallas/CAS Workshop onDesign, Applications, Integration and Software, DCAS-06

Volumn , Issue , 2006, Pages 87-90

  Vamvakos, Socrates D ^a   Staszewski, Robert Bogdan ^a   Sheba, Mahbuba ^a   Waheed, Khurram ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY CONVERTERS; JITTER; PHASE LOCKED LOOPS; SOFTWARE DESIGN;

ANALYTICAL RESULTS; EXACT ANALYSIS; NOISE ANALYSIS; PHASE LOCKED LOOP (PLL) ARCHITECTURE; PHASE-FREQUENCY DETECTOR (PFD); REFERENCE CLOCKS; SINUSOIDAL NOISE; TIME-TO-DIGITAL CONVERTER (TDC);

DIGITAL ARITHMETIC;

EID: 46249110576     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DCAS.2006.321040     Document Type: Conference Paper

References (4)

1. Staszewski, R.B., Muhammad, K., Leipold, D. et al., "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS", IEEE J. of Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, Dec. 2004.
2. R. B. Staszewski, Wallberg, J.L., Rezeq, S., et al., "All-Digital PLL and Transmitter for Mobile Phones", IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2481, Dec. 2005.
3. Staszewski, R.B., Vemulapalli, S., Vallur, P., Wallberg, J., Balsara, P.T., "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS", IEEE Trans. Circuits Syst. II, vol. 53, no. 3, pp. 220-224, Mar. 2006.
4. R. M. Gray, "Quantization Noise Spectra," IEEE Trans. Inform. Theory, vol. 36, pp.1220-1244, Nov. 1990.