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All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS
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Noise analysis of time-to-digital converter in all-digital PLLs
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S. D. Vamvakos, R. B. Staszewski, M. Sheba, and K. Waheed, "Noise analysis of time-to-digital converter in all-digital PLLs," Proc. of Fifth IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS-06), pp. 87 90, Oct. 2006, Dallas, TX.
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A low-noise, wide-BW 3.6GHz digital SA fractional-N synthesizer with a noise-shaping timeto-digital converter and quantization noise cancellation
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A low-noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution
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J. Tangudu, S. Gunturi, S. Jalan, J. Janardhanan, R. Ganesan, D. Sahu, K. Waheed, J. Wallberg, R. B. Staszewski, "Quantization noise improvement of time to digital converter (TDC) for ADPLL," Proc. of 2009 IEEE Intl. Symp. on Circuits and Systems, pp. 1020-1023, May 2009.
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1.3 v 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
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R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. on Circuits and Systems II, vol. 53, no. 3, pp. 220-224, Mar. 2006.
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Event-driven simulation and modeling of phase noise of an RF oscillator
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R. B. Staszewski, C. Fernando, and P. T. Balsara, "Event-driven simulation and modeling of phase noise of an RF oscillator," IEEE Trans. on Circuits and Systems I, vol. 52, no. 4, pp. 723 733, Apr. 2005.
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I. L. Syllaios, R. B. Staszewski, and P. T. Balsara, "Time-domain modeling of an RF all-digital PLL," IEEE Trans. on Circuits and Systems II, vol. 55, no. 6, pp. 601-604, Jun. 2008.
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