An all-digital offset PLL architecture

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2010, Pages 17-20

  Staszewski, Robert Bogdan ^b   Vemulapalli, Sudheer ^a   Waheed, Khurram ^a  

^a TEXAS INSTRUMENTS   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TRANSCEIVERS; DIGITAL IMPLEMENTATION; DIGITAL OFFSETS; FINITE RESOLUTION; FREQUENCY REFERENCE; HARDWARE OVERHEADS; INTEGER-N; LOOP FILTER; PARASITIC COUPLINGS; PHASE COMPARISON; PHASE DETECTION; QUANTIZATION ENERGY; QUANTIZATION NOISE; REFERENCE FREQUENCY; RF OSCILLATOR; SPURIOUS TONES; TIME TO DIGITAL CONVERTERS;

DIGITAL INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; INTEGRATED CIRCUITS; RADIO; RADIO WAVES;

PHASE LOCKED LOOPS;

EID: 77954485093     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2010.5477376     Document Type: Conference Paper

References (10)

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