Spurious free time-to-digital conversion in an ADPLL using short dithering sequences

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Waheed, Khurram ^a   Sheba, Mahbuba ^a   Staszewski, Robert Bogdan ^b   Dulger, Fikret ^a   Vamvakos, Socrates D ^a  

^a TEXAS INSTRUMENTS   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

All digital PLL (ADPLL); Dithering; Limit cycles; Phase error; Quantization; Short dither sequences; Time to digital converter (TDC)

Indexed keywords

ALL-DIGITAL PLL; DITHERING; LIMIT CYCLE; PHASE ERROR; QUANTIZATION; SHORT DITHER SEQUENCES; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; PHASE LOCKED LOOPS; SIGNAL PROCESSING;

ANTENNA PHASED ARRAYS;

EID: 78649880945     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617430     Document Type: Conference Paper

References (11)

1. R. B. Staszewski, Wallberg, J.L., Rezeq, S., et al., "All-Digital PLL and Transmitter for Mobile Phones", IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2481, Dec. 2005.
2. Staszewski, R.B., Vemulapalli, et al., "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS", IEEE Trans. Circuits Syst. II, vol. 53, no. 3, pp. 220 - 224, Mar. 2006.
3. R. M. Gray, "Quantization Noise Spectra," IEEE Trans. Inform. Theory, vol. 36, pp.1220-1244, Nov. 1990.
4. R. Tonietto, E. Zuffetti and R. Castello, "A 2MHz bandwidth low noise RF all digital PLL with 12ps resolution time-to-digital converter," Proc. of European Solid-State Circuits Conf., pp. 150-153, Sept. 2006.
5. C.-M. Hsu, M. Z. Strayer and M. H. Perrott, "A low-noise, wide-BW 3.6GHz digital ΣΔ fractional-N synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation," Proc. of IEEE Solid-State Circuits Conf., pp. 340-341, Feb. 2008.
6. C. W. Wu, E. Temporiti, D. Baldi and F. Svelto, "A 3GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction," Proc. of IEEE Solid-State Circuits Conf., pp. 344-345, Feb. 2008.
7. M. Lee, M. Heidari, A. Abidi, "A low-noise wideband digital phase locked loop based on a new time-to-digital converter with sub-picosecond resolution," VLSI Symp on Circuits, pp. 112-113, 2008.
8. J. Tangudu, S. Gunturi, S. Jalan, et al., "Quantization noise improvement of time to digital converter (TDC) for ADPLL," Proc. of 2009 IEEE Intl. Symp. on Circuits and Systems, pp. 1020-1023, May 2009.
9. R. Staszewski, K. Waheed, et al., "Elimination of Spurious Noise due to Time-to-Digital Converter," IEEE Dallas Circuits and Systems Workshop, Oct. 2009.
10. S. D. Vamvakos; R. B. Staszewski; M. Sheba and K. Waheed; "Noise Analysis of Time-to-Digital Converter in All-Digital PLLs" in 2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, 2006, Page(s): 87 - 90
11. A. Peterchev, S. Sanders, "Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters," IEEE Transactions on Power Electronics, pp. 301-308, Jan. 2003.