A 3GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 344-346

  Weiltin Wu, Colin ^a,b   Temporiti, Enrico ^c   Baldi, Daniele ^c   Svelto, Francesco ^b  

^a Och Spine at New York Presbyterian Hospitals   (United States)

^b UNIVERSITY OF PAVIA   (Italy)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; PHASE LOCKED LOOPS; SIGNAL PROCESSING;

65NM CMOS; ALL-DIGITAL PLL; BANDWIDTH CONTROL; FRACTIONAL-N; FREQUENCY RESOLUTIONS; MISMATCH CALIBRATION; MISMATCH CORRECTION; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS;

EID: 49549112279     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523198     Document Type: Conference Paper

References (3)

1. R. B. Staszewski, J. L. Wallberg, S. Rezeq et al., "All Digital PLL and Transmitters for Mobile Phones," IEEE J. Solid-State Circuits, pp. 2469-2482, Dec. 2005.
2. R. Tonietto, E. Zuffetti, R. Castello et al., "A 3MHz Bandwidth Low Noise RF all Digital PLL with 12ps Resolution Time to Digital Converter," Proc. ESSCIRC, pp.150-153, Sept.2006.
3. J. Doernberg, H-S. Lee and D. A. Hodges, "Full-Speed Testing of A/D Converters", IEEE J. Solid-State Circuits, pp. 820-827, Dec. 1984.