Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 69-80

  Mishra, Asit K ^a   Dong, Xiangyu ^a   Sun, Guangyu ^a   Xie, Yuan ^a   Vijaykrishnan, N ^a   Das, Chita R ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Design; Experimentation; Measurement; Performance

Indexed keywords

3D ARCHITECTURES; ARCHITECTURAL LEVELS; CACHE ACCESS; CACHE ARCHITECTURE; EXPERIMENTATION; HIGH DENSITY; LATENCY REDUCTION; LOW LEAKAGE; MAIN MEMORY; MEMORY TECHNOLOGY; MULTI CORE; MULTICORE ARCHITECTURES; MULTITHREADED; NONVOLATILITY; ON-CHIP CACHE; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; PERFORMANCE; WRITE OPERATIONS; DESCRIPTORS; RESISTIVE RAMS;

MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; RANDOM ACCESS STORAGE; THREE DIMENSIONAL; DESIGN; MEASUREMENTS; THREE DIMENSIONAL COMPUTER GRAPHICS;

CACHE MEMORY;

EID: 80052533056     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000074     Document Type: Conference Paper

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