Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 1, Issue 2, 2011, Pages 173-182

  Meinerzhagen, Pascal ^a   Sherazi, S M Yasser ^b   Burg, Andreas ^a   Rodrigues, Joachim Neves ^b  

^a EPFL   (Switzerland)

^b LUND UNIVERSITY   (Sweden)

Author keywords

Embedded memory; flip flop array; latch array; low power; process parameter variations; reliability; sub VT operation

Indexed keywords

EMBEDDED MEMORIES; FLIP-FLOP ARRAY; LATCH ARRAY; LOW POWER; PROCESS PARAMETER VARIATIONS; SUB-VT OPERATION;

ARCHITECTURE; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; LOGIC DESIGN; MEMORY ARCHITECTURE;

STATIC RANDOM ACCESS STORAGE;

EID: 80052048123     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2011.2162159     Document Type: Article

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