A <1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 253-258

  Rodrigues, Joachim Neves ^a   Akgun, Omer Can ^a   Öwall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CARDIAC PACEMAKERS; CLOCK RATE; CMOS TECHNOLOGY; ENERGY ESTIMATION; ENERGY MINIMA; HARDWARE IMPLEMENTATIONS; SIMULATION RESULT; STANDARD-CELL; SUBTHRESHOLD; SUPPLY VOLTAGES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; HARDWARE; PACEMAKERS; THRESHOLD VOLTAGE; VLSI CIRCUITS; WAVELET ANALYSIS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 78650950113     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642669     Document Type: Conference Paper

References (12)

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