A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Volumn , Issue , 2010, Pages 313-316

  Roth, C ^a   Meinerzhagen, P ^a   Studer, C ^a   Burg, A ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; BLOCK LENGTHS; CLOCK FREQUENCY; CODE MATRICES; CORE AREA; DECODING ITERATION; IEEE 802.11N; LDPC DECODER; LOW DENSITY PARITY CHECK; LOW POWER; MAXIMUM THROUGH-PUT; MIN-SUM ALGORITHM; OPERATING VOLTAGE; QUASI-CYCLIC; REGISTER TRANSFER LEVEL; RUNTIMES; WLAN STANDARDS;

COMMUNICATION CHANNELS (INFORMATION THEORY); ITERATIVE DECODING; STANDARDS;

ENERGY EFFICIENCY;

EID: 79952831255     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2010.5716618     Document Type: Conference Paper

References (9)

1. R. Gallager, "Low density parity check codes," Trans. of the IRE Prof. Group on Inf. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
2. IEEE Unapproved Draft Std P802.11n/D11.0, Jun. 2009.
3. E. Sharon, S. Litsyn, and J. Goldberger, "An efficient message-passing schedule for LDPC decoding," in Proc. 23rd IEEE Convention of Electrical and Electronics Engineers in Israel, Sep. 2004, pp. 223-226.
4. J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Y. Hu, "Reduced-complexity decoding of LDPC codes," IEEE Trans. on Comm., vol. 53, no. 7, pp. 1288-1299, Aug. 2005.
5. C. Studer, N. Preyss, C. Roth, and A. Burg, "Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes," in Proc. 42nd Asilomar Conf. on Signals, Systems and Computers, Oct. 2008, pp. 1137-1142.
6. P. Meinerzhagen, C. Roth, and A. Burg, "Towards generic low-power area-efficient standard cell based memory architectures," in Proc. 53rd IEEE Int'l. Midwest Symp. on Circuits and Systems, Aug. 2010, pp. 129-132.
7. T.-C. Kuo and A. Willson, "A flexible decoder IC for WiMAX QC-LDPC codes," in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2008, pp. 527-530.
8. Y. Sun and J. R. Cavallaro, "A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards," in Proc. IEEE Int'l. SOC Conf., Sep. 2008, pp. 367-370.
9. X.-Y. Shih, C.-Z. Zhan, and A.-Y. Wu, "A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices," in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 369-372.