Exploring partitioning methods for 3D networks-on-chip utilizing adaptive routing model

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 73-80

  Ebrahimi, Masoumeh ^a   Daneshtalab, Masoud ^a   Liljeberg, Pasi ^a   Plosila, Juha ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

3D IC DESIGN; 3D MESHES; ADAPTIVE ROUTING; ALTERNATIVE PATH; HAMILTONIAN PATH; MULTICAST COMMUNICATION; MULTICAST OPERATIONS; MULTICAST TRAFFIC; MULTIPROCESSOR SYSTEM ON CHIPS; NETWORK LATENCIES; NETWORKS ON CHIPS; PARALLEL APPLICATION; PARTITIONING METHODS; RECURSIVE PARTITIONING; THREE DIMENSIONAL (3D) INTEGRATION; UNICAST;

ALGORITHMS; MESH NETWORKING; MICROPROCESSOR CHIPS; MULTICASTING; NETWORK ROUTING; REGRESSION ANALYSIS;

THREE DIMENSIONAL;

EID: 79960316692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999958     Document Type: Conference Paper

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