Scalability of network-on-chip communication architecture for 3-D meshes

Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009

Volumn , Issue , 2009, Pages 114-123

  Weldezion, Awet Yemane ^a   Grange, Matt ^b   Pamunuwa, Dinesh ^b   Lu, Zhonghai ^a   Jantsch, Axel ^a   Weerasekera, Roshan ^b   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b LANCASTER UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

3D NETWORKS; COMMUNICATION ARCHITECTURES; COMMUNICATION SCHEMES; COMMUNICATION TOPOLOGIES; CYCLE ACCURATE; DESIGN CONSTRAINTS; DESIGN GUIDELINES; GLOBAL INTERCONNECT DELAY; INTEGRATED ELECTRONICS; NETWORK ON CHIP; TECHNOLOGY SOLUTIONS; THROUGH SILICON VIAS; TRAFFIC PATTERN;

BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NETWORK PERFORMANCE; ROUTERS; SCALABILITY; SYSTEMS ENGINEERING; THREE DIMENSIONAL;

COMMUNICATION;

EID: 70349808489     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2009.5071459     Document Type: Conference Paper

References (18)

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