Tightly-coupled multi-layer topologies for 3-D NoCs

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2007, Pages

  Matsutani, Hiroki ^a   Koibuchi, Michihiro ^b   Amano, Hideharu ^a  

^a KEIO UNIVERSITY   (Japan)

^b NATIONAL INSTITUTE OF INFORMATICS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; ELECTRIC NETWORK TOPOLOGY; ELECTRON BEAM LITHOGRAPHY; ENERGY POLICY; HEAT STORAGE; NETWORK ARCHITECTURE; ROUTING ALGORITHMS; THREE DIMENSIONAL; THROUGHPUT; TOPOLOGY; WIRE;

3-D ICS; BOTTOM LAYERS; CHIP SIZES; CONNECTED NETWORKS; COST PERFORMANCES; CROSSBAR SWITCHING; DEADLOCK FREEDOM; ENERGY CONSUMPTION.; HIGH-DENSITY; HIGH-THROUGHPUT (HT); INTERNATIONAL CONFERENCES; MULTILAYER (ML); NETWORK CONNECTIVITY; NETWORK LAYERS; NETWORK TOPOLOGIES; PACKET TRANSFER; PARALLEL PROCESSING; PLANAR TOPOLOGY; THREE DIMENSIONAL (3D) NETWORKS; TIGHTLY-COUPLED; WIRE DELAYS; WIRE LENGTHS;

COMPUTER ARCHITECTURE;

ALGORITHMS; COMPUTER CHIPS; ELECTRIC CIRCUITS; ELECTRON BEAMS; LITHOGRAPHY; THREE DIMENSIONAL DESIGN; WIRE;

EID: 47249106925     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2007.79     Document Type: Conference Paper

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