Toward system on chip (SoC) development using FinFET technology: Challenges, solutions, process co-development & optimization guidelines

IEEE Transactions on Electron Devices

Volumn 58, Issue 6, 2011, Pages 1597-1607

  Shrivastava, Mayank ^a   Mehta, Ruchit ^b   Gupta, Shashank ^c   Agrawal, Nidhi ^c   Baghini, Maryam Shojaei ^c   Sharma, Dinesh Kumar ^c   Schulz, Thomas ^a   Arnim, Klaus ^a   Molzer, Wolfgang ^a   Gossner, Harald ^a   Rao, V Ramgopal ^c  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Extremely thin SOI (ETSOI); FinFET; implant free process; ion implantation and system on chip (SoC); process co optimization; scaling

Indexed keywords

FINFET; IMPLANT-FREE PROCESS; PROCESS CO-OPTIMIZATION; SCALING; THIN SOI;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; GATES (TRANSISTOR); INTEGRATED CIRCUITS; ION IMPLANTATION; MICROPROCESSOR CHIPS; MOS DEVICES; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 79957660056     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2123100     Document Type: Article

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