A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Jan, C H ^a   Agostinelli, M ^a   Buehler, M ^a   Chen, Z P ^a   Choi, S J ^a   Curello, G ^a   Deshpande, H ^a   Gannavaram, S ^a   Hafez, W ^a   Jalan, U ^a   Kang, M ^a   Kolar, P ^a   Komeyli, K ^a   Landau, B ^a   Lake, A ^a   Lazo, N ^a   Lee, S H ^a   Leo, T ^a   Lin, J ^a   Lindert, N ^a   Ma, S ^a   McGill, L ^a   Meining, C ^a   Paliwal, A ^a   Park, J ^a   Phoa, K ^a   Post, I ^a   Pradhan, N ^a   Prince, M ^a   Rahman, A ^a   Rizk, J ^a   Rockford, L ^a   Sacks, G ^a   Schmitz, A ^a   Tashiro, H ^a   Tsai, C ^a   Vandervoorn, P ^a   Xu, J ^a   Yang, L ^a   Yeh, J Y ^a   Yip, J ^a   Zhang, K ^a   Zhang, Y ^a   Bai, P ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED MEMORIES; FEATURE SPACE; GATE LEAKAGES; GATE TRANSISTORS; HIGH DENSITY; HIGH PRECISION; HIGH QUALITY; HIGH VOLTAGE TOLERANT; HIGH-K GATE DIELECTRICS; I/O DEVICE; LEADING EDGE; LOW VOLTAGES; MIX-AND-MATCH; NOISE ISOLATION; NOISE MITIGATION; OTP FUSE; PASSIVE ELEMENTS; SOC PLATFORMS; TRANSISTOR ARCHITECTURE; ULTRA LOW POWER;

ELECTRON DEVICES; GATE DIELECTRICS; GATES (TRANSISTOR); LARGE SCALE SYSTEMS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

TRANSISTORS;

EID: 77952328803     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424258     Document Type: Conference Paper

References (5)

1. K. Mistry et al, IEDM Tech Dig., pp. 247-250, 2007
2. C. Auth et al, VLSI Symp. Proc., pp. 128-129, 2008
3. S. Natarajan et al, IEDM Tech. Dig., pp. 941-943, 2008
4. C.-H. Jan et al, IEDM Tech. Dig., pp. 637-640, 2008
5. C.-H. Jan et al, IEDM Tech Dig., pp. 65-68, 2005