First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Merelle T ^a   Curatola, G ^a   Nackaerts, A ^a   Collaert, N ^b   Van Dal, M J H ^a   Doornbos, G ^a   Doorn, T S ^c   Christie, P ^a   Vellianitis, G ^a   Duriez, B ^a   Duffy, R ^a   Pawlak, B J ^a   Voogt, F C ^c   Rooyackers, R ^b   Witters, L ^b   Jurczak, M ^b   Lander, R J P ^a  

^a NXP TSMC Research Center   (Belgium)

^b IMEC   (Belgium)

^c NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

FINFETS; GATE CONTROLS; OPTIMIZATION STRATEGIES; SOI FINFETS; SRAM DESIGNS; SUBSTANTIAL REDUCTIONS; UNDOPED CHANNELS;

ELECTRON DEVICES; FIELD EFFECT TRANSISTORS; LOGIC DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 64549103332     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796662     Document Type: Conference Paper

References (8)

1. C. Fenouillet-Beranger et al., IEDM 2007.
2. M.J.H. van Dal et al., VLSI Tech. 2007.
3. G. Vellianitis, IEDM 2007.
4. R.V. Joshi et al., ESSDERC 2004.
5. M. Mueller et al., SSDM 2007.
6. N. Collaert et al., ICICDT 2008.
7. A.V-Y. Thean et al., IEDM 2006.
8. T.Y. Hoffmann et al., IEDM 2005.