A 25-nm gate-length FinFet transistor module for 32nm node

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Chang, Chang Yun ^a   Lee, Tsung Lin ^a   Wann, Clement ^a   Lai, Li Shyue ^a   Chen, Hung Ming ^a   Yeh, Chih Chieh ^a   Chang, Chih Sheng ^a   Ho, Chia Cheng ^a   Sheu, Jyh Cherng ^a   Kwok, Tsz Mei ^a   Yuan, Feng ^a   Yu, Shao Ming ^a   Hu, Chia Feng ^a   Shen, Jeng Jung ^a   Liu, Yi Hsuan ^a   Chen, Chen Ping ^a   Chen, Shin Chih ^a   Chen, Li Shiun ^a   Chen, Leo ^a   Chiu, Yuan Hung ^a   Fu, Chu Yun ^a   Huang, Ming Jie ^a   Huang, Yu Lien ^a   Hung, Shih Ting ^a   Liaw, Jhon Jhy ^a   Lin, Hsien Chin ^a   Lin, Hsien Hsin ^a   Lin, L T S ^a   Lin, Shyue Shyh ^a   Mii, Yuh Jier ^a   Eric, Ou Yang ^a   Shieh, Ming Feng ^a   Su, Chien Chang ^a   Tai, Shih Peng ^a   Tao, Hun Jan ^a   Tsai, Ming Huan ^a   Tseng, Kai Ting ^a   Wang, Kin Weng ^a   Wang, Shiang Bau ^a   Xu, Jeff J ^a   Yang, Fu Kai ^a   Yang, Shu Tine ^a   Yeh, Chen Nan ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

32-NM NODE; DOUBLE-GATE TRANSISTOR; DRIVE CURRENTS; FIN PITCH; GATE LENGTH; HIGH DRIVE CURRENT; LAYOUT AREA; LOW POWER; PLANAR DEVICES; RANDOM DOPANT FLUCTUATION; REAL ESTATE; TRANSISTOR WIDTH;

ELECTRON DEVICES; FINS (HEAT EXCHANGE); NANOTECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

TRANSISTORS;

EID: 77952372594     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424367     Document Type: Conference Paper

References (5)

1. H.S. P. Wong et. al., IEEE Proceedings 1999, p.537
2. M.J.H van Dal et. al., VLSI Symp. 2007, p.110
3. G. Vellianitis et. al., IEDM 2007, p.681
4. J. Kavalieros et. al., VLSI Symp. 2006, p.50
5. A. Kaneko et. al., IEDM 2006, p893