VESPA: Variability emulation for system-on-chip performance analysis

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 2-7

  Kozhikkottu, Vivek J ^a   Venkatesan, Rangharajan ^a   Raghunathan, Anand ^a   Dey, Sujit ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

802.11 MAC; CLOCK FREQUENCY; EXECUTION PATHS; INDIRECT EFFECTS; INTER-DEPENDENCIES; MONTE CARLO; PERFORMANCE ANALYSIS; SHARED RESOURCES; STATISTICAL TIMING ANALYSIS; SYSTEM LEVEL SIMULATION; SYSTEM LEVELS; SYSTEM ON CHIPS; SYSTEM-LEVEL PERFORMANCE; SYSTEM-ON-CHIP ARCHITECTURE; THREE PHASIS; VARIATION ANALYSIS; VARIATION-AWARE DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DESIGN; MOTION PICTURE EXPERTS GROUP STANDARDS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 79957567002     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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