System-on-chip power management considering leakage power variations

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 877-882

  Chandra, Saumya ^a,b   Lahiri, Kanishka ^b   Raghunathan, Anand ^b   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

Low power design; Power management; Process variations; System on chip

Indexed keywords

ARM PROCESSOR; LEAKAGE POWER VARIATIONS; LOW POWER DESIGN; POWER MANAGEMENT; PROCESS VARIATIONS; SYSTEM ON CHIP;

DESIGN AIDS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; OPTIMIZATION;

ENERGY MANAGEMENT;

EID: 34547365822     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375287     Document Type: Conference Paper

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