Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations

IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM

Volumn , Issue , 2008, Pages

  Wang, Feng ^a   Xie, Yuan ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER NETWORKS; DESIGN; DISTRIBUTED PARAMETER NETWORKS; GAS DYNAMIC LASERS; INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING; SCHEDULING ALGORITHMS; STATISTICAL METHODS;

MULTI-PROCESSOR SYSTEM-ON-CHIP; PARALLEL AND DISTRIBUTED PROCESSING; PROCESS VARIATIONS; TASK ALLOCATION AND SCHEDULING;

PROCESS DESIGN;

EID: 51049111853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2008.4536424     Document Type: Conference Paper

References (10)

1. Shekhar Borkar. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro, 25(6):10-16, 2005.
2. A. Jerraya and W. Wolf. Multiprocessor systems-on-chips. Morgan Kaufmann Publishers, 2005.
3. K. A. Bowman, S. G. Duvall, and J. D. Meindl. Impact of Die-to-Die and Within Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration. Journal of Solid-State Circuits, pages 183-190, February 2002.
4. C. Clark. The greatest of a finite set of random variables. Operations Research, pages 145-162, 1961.
5. C. Hongliang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In International Conference on Computer Aided Design, pages 621-625, 2003.
6. G.C. Sih and E.A. Lee. A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures. IEEE Transactions on Parallel and Distributed Systems, 04(2):175-187, 1993.
7. K. Chopra, S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester. Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. International Conference on Computer-Aided Design, pages 1023-1028, November 2005.
8. Y. B. Li and J. Henkel. A framework for estimation and minimizing energy dissipation of embedded hw/sw systems. Design Automation Conference (DAC), pages 188-193, 1998.
9. Robert P. Dick. Embedded systems synthesis benchmarks suite (e3s). http://www.ece.northwestern.edu/dickrp/e3s/.
10. W-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Thermal-aware task allocation and scheduling for embedded systems. Design, Automation and Test in Europe Conference, pages 898-899, 2005.