Process variations aware robust on-chip bus architecture synthesis for MPSoCs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 2989-2992

  Pandey, Sujan ^a   Drechsler, Rolf ^b   Murgan, Tudor ^c,d   Glesner, Manfred ^c  

^a NXP SEMICONDUCTORS   (Netherlands)

^b UNIVERSITY OF BREMEN   (Germany)

^c DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^d QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARSENIC COMPOUNDS; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUITS; NONLINEAR PROGRAMMING; TECHNICAL PRESENTATIONS; WIRE;

PROCESS VARIATIONS;

BUSES;

EID: 51749092385     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4542086     Document Type: Conference Paper

References (14)

1. A. Andrei et al. Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time constrained systems. In proc. of ICCAD, pages 262-269, 2004.
2. Y. Cao et al. Mapping statistical process variations toward circuit performance variability: An analytical modeling approach. In proc. of DAC, pages 658-663, 2005.
3. M. Gasteier et al. Bus-based communication synthesis on system level. ACM Trans. of design automation electronic systems, pages 1-11, 1999.
4. H. F. Jyu et al. Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI systems, Vol. 1(No. 2):126-137, 1993.
5. D. Lyonnard et al. Automatic generation of application specific architectures for heterogeneous multiprocessor soc. In proc. of DAC, pages 518-523, 2001.
6. S. R. Nassif et al. Variation-aware analysis: Savior of the nanometer era? In proc. of DAC, pages 411-412, 2006.
7. Y. Nesterov and A. Nemirovskii. Interior-point polynomial algorithms in convex programming. Studies in Applied Mathematics, 1994.
8. M. Orshansky et al. Direct sampling methodology for statistical analysis of scaled cmos technologies. In IEEE Trans. on semiconductor manufacturing, Vol. 12(No. 4):403-408, 1999.
9. S. Pandey, C. Genz, and R. Drechsler. Co-synthesis of custom on-chip bus and memory for MPSoC architectures. In proc. of VLSISoC, pages 304-307, 2007.
10. S. Pandey and M. Glesner. Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic. In IEEE Tran. on VLSI systems, Vol. 15(No. 10):1111-1124, Oct. 2007.
11. S. Pasricha et al. FABSYN : Floorplan-aware bus architecture synthesis. IEEE Tran. on VLSI systems, Vol. 14(No. 3):241-253, 2006.
12. A. Pinto, L. P. Carloni, and A. V. Sangiovanni. Constraint driven communication synthesis. In proc. of DAC, pages 783-788, June 2002.
13. K. K. Rye and V. MooneyIII. Automated bus generation for multiprocessor soc design. IEEE TCAD, Vol. 23(No. 11):1531-1549, Nov. 2004.
14. T. Y. Yen and W. Wolf. Communication synthesis for distributed embedded systems. In proc. of ICCAD, pages 288-294, 1995.