Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 4, 2011, Pages 574-583

  Li, Xiao Chun ^a   Mao, Jun Fa ^a   Swaminathan, Madhavan ^b  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Complementary metal oxide semiconductor (CMOS); device models; interconnect; multiconductor transmission lines; noise analysis; signal integrity; timing analysis

Indexed keywords

COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; DEVICE MODELS; INTERCONNECT; MULTI-CONDUCTOR TRANSMISSION LINES; NOISE ANALYSIS; SIGNAL INTEGRITY; TIMING ANALYSIS;

BANDPASS FILTERS; CMOS INTEGRATED CIRCUITS; CROSSTALK; DELAY CIRCUITS; DIELECTRIC DEVICES; DRAIN CURRENT; ELECTRIC LINES; FINITE DIFFERENCE TIME DOMAIN METHOD; INTERCONNECTION NETWORKS; MAGNETIC FIELD MEASUREMENT; METAL ANALYSIS; NONLINEAR ANALYSIS; PIECEWISE LINEAR TECHNIQUES; SEMICONDUCTOR DEVICE MODELS; TIME DELAY; TIME VARYING NETWORKS; TRANSMISSION LINE THEORY;

TRANSIENT ANALYSIS;

EID: 79953117517     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2095650     Document Type: Conference Paper

References (46)

1. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.
2. T. Sakurai and A. R. Newton, "Alpha-power model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990. (Pubitemid 20701405)
3. S. Dutta, S. S. M. Shetti, and S. L. Lusky, "A comprehensive delay model for CMOS inverters," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 864-871, Aug. 1995.
4. L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, "Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices," IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 302-306, Feb. 1998. (Pubitemid 128576210)
5. J. Qian, S. Pullela, and L. Pillage, "Modeling the 'effective capacitance' for the RC interconnect of CMOS gates," IEEE Trans. Comput.-Aided Des., vol. 13, no. 12, pp. 1526-1535, Dec. 1994.
6. M. Hafed, M. Oulmane, and N. C. Rumin, "Delay and current estimation in a CMOS inverter with an RC load," IEEE Trans. Comput.-Aided Des., vol. 20, no. 1, pp. 80-89, Jan. 2001. (Pubitemid 32296866)
7. A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, "Modeling CMOS gates driving RC interconnect loads," IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., vol. 48, no. 4, pp. 413-418, Apr. 2001. (Pubitemid 32732782)
8. B. K. Kaushik, S. Sarkara, and R. P. Agarwala, "Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load," Integration, Very Large Scale Integr. J., vol. 40, no. 4, pp. 394-405, Jul. 2007. (Pubitemid 46783072)
9. J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Comput.-Aided Des., vol. 2, no. 3, pp. 202-211, Jul. 1983.
10. A. Kahng and S. Muddu, "An analytical delay model for RLC interconnects," IEEE Trans. Comput.-Aided Des., vol. 16, no. 2, pp. 1507-1514, Dec. 1997. (Pubitemid 127765027)
11. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore delay for RLC trees," IEEE Trans. Comput.-Aided Des., vol. 19, no. 1, pp. 83-97, Jan. 2000. (Pubitemid 30557236)
12. T. Sakurai, "Closed-form expressions for interconnect delay, coupling, and crosstalk in VLSIs," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993. (Pubitemid 23631445)
13. Y. Eo, W. R. Eisenstadt, J. Y. Jeong, and O.-K. Kwon, "A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design," IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 129-140, Jan. 2000. (Pubitemid 30565153)
14. L. Ding, D. Blaauw, and P. Mazumder, "Accurate crosstalk modeling for early signal integrity analysis," IEEE Trans. Comput.-Aided Des., vol. 22, no. 5, pp. 627-635, May 2003.
15. X. Bai, R. Chandra, S. Dey, and P. V. Srinivas, "Interconnect couplingaware driver modeling in static noise analysis for nanometer circuits," IEEE Trans. Comput.-Aided Des., vol. 23, no. 8, pp. 1256-1263, Aug. 2004.
16. J. A. Davis and J. D. Meindl, "Compact distributed RLC models, part I: Single line transient, time delay, and overshoot expressions," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2068-2077, Nov. 2000.
17. J. A. Davis and J. D. Meindl, "Compact distributed RLC models, part II: Coupled line transient expressions and peak crosstalk in multilevel networks," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2078- 2087, Nov. 2000.
18. K. Agarwal, D. Sylvester, and D. Blaauw, "Modeling and analysis of crosstalk noise in coupled RLC interconnects," IEEE Trans. Comput.- Aided Des., vol. 25, no. 5, pp. 892-901, May 2006.
19. C. R. Paul, "Incorporation of terminal constraints in the FDTD analysis of transmission lines," IEEE Trans. Electromagnetic Compatibility, vol. 36, no. 2, pp. 85-91, May 1994.
20. J. A. Roden, C. R. Paul, W. T. Smith, and S. D. Gedney, "Finitedifference, time-domain analysis of lossy transmission lines," IEEE Trans. Electromagnetic Compatibility, vol. 38, no. 1, pp. 15-24, Feb. 1996. (Pubitemid 126779851)
21. K. S. Kunz and R. J. Luebbers, The Finite Difference Time Domain Method in Electromagnetics. Boca Raton, FL: CRC Press, 1993.
22. J. E. Bracken, V. Raghavan, and R. A. Rohrer, "Interconnect simulation with asymptotic waveform evaluation (AWE)," IEEE Trans. Circuits Syst. I, vol. 39, no. 11, pp. 869-878, Nov. 1992. (Pubitemid 23623368)
23. Q. Xu, Z. F. Li, J. Wang, and J. F. Mao, "Transient analysis of lossy interconnects by modified method of characteristics," IEEE Trans. Circuits Syst. I, vol. 47, no. 3, pp. 363-375, Mar. 2000.
24. J.-F. Mao and Z.-F. Li, "Analysis of the time response of nonuniform multiconductor transmission lines with a method of equivalent cascaded network chain," IEEE Trans. Microw. Theory Tech., vol. 40, no. 5, pp. 948-954, May 1992.
25. V. A. Thomas, M. E. Jones, M. Piket-May, A. Taflove, and E. Harrigan, "The use of SPICE lumped circuits as sub-grid models for FDTD analysis," IEEE Microw. Guided Wave Lett., vol. 4, no. 5, pp. 141-143, May 1994.
26. N. Orhanovic and N. Matsui, "FDTD-SPICE analysis of high-speed cells in silicon integrated circuits," in Proc. Electron. Compon. Technol. Conf., May 2002, pp. 347-352. (Pubitemid 34691967)
27. B. Zhong, T. Hu, D. Fu, S. L. Dvorak, and J. L. Prince, "A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures," IEEE Trans. Comput.-Aided Des., vol. 24, no. 8, pp. 1250-1261, Aug. 2005. (Pubitemid 41118746)
28. A. Dounavis and V. A. Pothiwala, "Passive closed-form transmission line macromodel using method of characteristics," IEEE Trans. Adv. Packag., vol. 31, no. 1, pp. 190-202, Feb. 2008. (Pubitemid 351359283)
29. C. Chen, D. Saraswat, R. Achar, E. Gad, M. S. Nakhla, and M. C. E. Yagoub, "Passivity compensation algorithm for methodof- characteristics-based multiconductor transmission line interconnect macromodels," IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 8, pp. 1061-1072, Aug. 2009.
30. B. Zhong, D. Steven, and P. John, "Transient simulation of lossy interconnects based on a dispersive hybrid phase-pole macromodel," IEEE Trans. Adv. Packag., vol. 30, no. 2, pp. 321-334, May 2007. (Pubitemid 46852059)
31. A. Odabasioglu, M. Celik, and L. T. Pilleggi, "PRIMA: Passive reducedorder interconnect macromodeling algorithm," IEEE Trans. Comput.- Aided Des., vol. 17, no. 8, pp. 645-653, Aug. 1998.
32. A. Dounavis, R. Achar, and M. Nakhla, "A general class of passive macromodels for lossy multiconductor transmission lines," IEEE Trans. Microw. Theory Tech., vol. 49, no. 10, pp. 1686-1696, Oct. 2001. (Pubitemid 33008186)
33. A. C. Cangellaris, S. Pasha, J. L. Prince, and M. Celik, "A new discrete time-domain model for passive model order reduction and macromodeling of high-speed interconnections," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 356-364, Aug. 1999. (Pubitemid 30559657)
34. Q. Yu, J. M. L. Wang, and E. S. Kuh, "Passive multipoint moment matching model order reduction algorithm on multiport distributed interconnect networks," IEEE Trans. Circuits Syst. I, vol. 46, no. 1, pp. 140-160, Jan. 1999.
35. E. Gad and M. Nakhla, "Efficient simulation of nonuniform transmission lines using integrated congruence transform," IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 5, pp. 1307-1320, May 2004. (Pubitemid 40121141)
36. G. Antonini, D. Deschrijver, and T. Daene, "Broadband rational macromodeling based on the adaptive frequency sampling algorithm and the partial element equivalent circuit method," IEEE Trans. Electromagnetic Compatibility, vol. 50, no. 1, pp. 128-137, Feb. 2008. (Pubitemid 351404511)
37. E.-X. Liu, E. P. Li, and Z. X. Shen, "Finite-difference time-domain macromodel for simulation of electromagnetic interference at high-speed interconnects," IEEE Trans. Magnetics, vol. 41, no. 1, pp. 65-71, Jan. 2005.
38. C. R. Paul, "A SPICE model for multiconductor transmission lines excited by an incident electromagnetic field," IEEE Trans. Electromagnetic Compatibility, vol. 36, no. 4, pp. 342-354, Nov. 1994.
39. H. Xie, J. Wang, R. Fan, and Y. Liu, "A hybrid FDTD-SPICE method for transmission lines excited by a nonuniform incident wave," IEEE Trans. Electromagnetic Compatibility, vol. 36, no. 4, pp. 342-354, Nov. 2009.
40. W. Sui, D. A. Christensen, and C. H. Durney, "Extending the 2-D FDTD method to hybrid electromagnetic systems with active and passive lumped elements," IEEE Trans. Microw. Theory Tech., vol. 40, no. 4, pp. 724-730, Apr. 1992.
41. M. Piket-May, A. Taflove, and J. Baron, "FDTD modeling of digital signal propagation in 3-D circuits with passive and active loads," IEEE Trans. Microw. Theory Tech., vol. 42, no. 8, pp. 1514-1523, Aug. 1994.
42. C. Kuo, B. Houshmand, and T. Itoh, "Full-wave analysis of packaged microwave circuits with active and nonlinear devices: An FDTD approach," IEEE Trans. Microw. Theory Tech., vol. 45, no. 5, pp. 819-826, May 1997. (Pubitemid 127826889)
43. M. Fujii, H. Murase, and S. Kobayashi, "FDTD modeling of switching noise in multilayered digital circuits with CMOS inverters and passive lumped elements," in Proc. IEEE MTT-S Int. Microwave Symp. Dig., vol. 3. Jun. 1996, pp. 1787-1790.
44. S. G. Talocia, I. S. Stievano, and F. G. Canavero, "Hybridization of FDTD and device behavioral-modeling techniques," IEEE Trans. Electromagnetic Compatibility, vol. 45, no. 1, pp. 31-42, Feb. 2003.
45. B. K. Kaushik and S. Sarkar, "Crosstalk analysis for a CMOS-gatedriven coupled interconnects," IEEE Trans. Comput.-Aided Des., vol. 27, no. 6, pp. 1150-1154, Jun. 2008. (Pubitemid 351715249)
46. X. Li, J. Mao, and M. Swaminathan, "Accurate analysis of CMOS inverter driving transmission line based on FDTD," in Proc. IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2009, pp. 1573-1576.