Crosstalk analysis for a CMOS-gate-driven coupled interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 6, 2008, Pages 1150-1154

  Kaushik, Brajesh Kumar ^a   Sarkar, Sankar ^b  

^a GB Pant Engineering College   (India)

^b Mody College of Engineering and Technology   (India)

Author keywords

Coupling; Crosstalk noise; Inductance; Integrated circuit interconnect; Signal integrity; Transmission lines

Indexed keywords

CMOS INTEGRATED CIRCUITS; INDUCTANCE; MOSFET DEVICES; SPICE;

CROSSTALK NOISE; SIGNAL INTEGRITY;

CROSSTALK;

EID: 44149127763     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.923259     Document Type: Article

References (4)

1. J. M. Rabaey, Digital Integrated Circuits, A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.
2. K. Agarwal, D. Sylvester, and D. Blaauw, "Modeling and analysis of crosstalk noise in coupled RLC interconnects," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 5, pp. 892-901, May 2006.
3. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
4. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.