Modeling CMOS gates driving RC interconnect loads

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 4, 2001, Pages 413-418

  Chatzigeorgiou, Alexander ^a   Nikolaidis, Spiridon ^a   Tsoukalas, Ioannis ^a  

^a ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

Modeling; Propagation delay; Short circuit power

Indexed keywords

CALCULATIONS; CAPACITANCE; COMPUTER SIMULATION; DIFFERENTIAL EQUATIONS; GATES (TRANSISTOR); MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES; SHORT CIRCUIT CURRENTS; WAVEFORM ANALYSIS;

COUPLING CAPACITANCE; INTERCONNECT LOADS; PROPAGATION DELAY; SHORT-CIRCUIT POWER DISSIPATION; SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0035300255     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.933808     Document Type: Article

References (12)

1. Approximation of wiring delay in MOSFET LSI
2. Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
3. CMOS circuit speed and buffer optimization
4. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
5. Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices
6. Repeater design to reduce delay and power in resistive interconnect
7. Modeling the "effective capacitance" for the RC interconnect of CMOS gates
8. Performance computation for precharacterized CMOS gates with RC loads
9. Estimation of short-circuit power dissipation for static CMOS gates driving a CRC π load
10. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
11. Estimation of short-circuit power dissipation for static CMOS gates