Delay and current estimation in a CMOS inverter with an RC load

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 1, 2001, Pages 80-89

  Hafed, Mohamed ^a,b   Oulmane, Mourad ^b   Rumin, Nicholas C ^a,b  

^a IEEE   (Canada)

^b MCGILL UNIVERSITY   (Canada)

Author keywords

CMOS; Current; Delay; Digital integrated circuits; Interconnections; Inverter; RC load

Indexed keywords

CAPACITANCE LOAD;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; ELECTRIC LOADS; ITERATIVE METHODS; RESISTORS; TRANSISTORS;

ELECTRIC INVERTERS;

EID: 0035064970     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.905677     Document Type: Article

References (17)

1. Inverter models of CMOS for gates supply current and delay evaluation
2. An analytical model for current, delay, and power of submicron CMOS logic circuits
3. Delay models for CMOS, BiCMOS, and BiNMOS circuits and their applications for timing simulations
4. Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices
5. Modeling technique for CMOS gates
6. Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
7. Interconnect simulation with asymptotic waveform evaluation (AWE)
8. Modeling the effective capacitance for the RC interconnect of CMOS gates
9. Combining RC-Interconnect effects with nonlinear MOS macromodels
10. Analytical fast timing simulation of MOS circuits driving RC interconnects
11. A gate-delay model for high-speed CMOS circuits
12. Calculating worst-case gate delays due to dominant capacitance coupling
13. CMOS gate delay models for general RLC loading
14. Delay and power expressions for a CMOS inverter driving a resistive-capacitive load
15. Performance computation for precharacterized CMOS gates with RC loads
16. CMOS inverter current and delay model incorporating interconnect effects