메뉴 건너뛰기




Volumn 22, Issue 5, 2003, Pages 627-634

Accurate crosstalk noise modeling for early signal integrity analysis

Author keywords

Crosstalk noise; Digital CMOS circuits; Interconnect; Noise estimation; Signal integrity

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; CROSSTALK; INTERCONNECTION NETWORKS; LUMPED PARAMETER NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION; SPURIOUS SIGNAL NOISE;

EID: 0037515478     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.810741     Document Type: Article
Times cited : (38)

References (20)
  • 4
    • 0032643013 scopus 로고    scopus 로고
    • Reducing cross-coupling among interconnect wires in deep-submicron datapath design
    • J.-S. Yim and C.-M. Kyung, "Reducing cross-coupling among interconnect wires in deep-submicron datapath design," in Proc. Design Automation Conf., June 1999, pp. 485-490.
    • Proc. Design Automation Conf., June 1999 , pp. 485-490
    • Yim, J.-S.1    Kyung, C.-M.2
  • 8
    • 0025414182 scopus 로고
    • Asymptotic waveform evaluation for timing analysis
    • Apr.
    • L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
    • (1990) IEEE Trans. Computer-Aided Design , vol.9 , pp. 352-366
    • Pillage, L.T.1    Rohrer, R.A.2
  • 9
    • 0029308198 scopus 로고
    • Efficient linear circuit analysis by Padé approximation via the Lanczos process
    • May
    • P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Padé approximation via the Lanczos process," IEEE Trans. Computer-Aided Design, vol. 14, pp. 639-649, May 1995.
    • (1995) IEEE Trans. Computer-Aided Design , vol.14 , pp. 639-649
    • Feldmann, P.1    Freund, R.W.2
  • 10
    • 0032139262 scopus 로고    scopus 로고
    • PRIMA: Passive reduced-order interconnect macromodeling algorithm
    • Aug.
    • A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Computer-Aided Design, vol. 17, pp. 645-654, Aug. 1998.
    • (1998) IEEE Trans. Computer-Aided Design , vol.17 , pp. 645-654
    • Odabasioglu, A.1    Celik, M.2    Pileggi, L.T.3
  • 11
    • 0032681122 scopus 로고    scopus 로고
    • Harmony: Static noise analysis of deep submicron digital integrated circuits
    • Aug.
    • K. L. Shepard, V. Narayanan, and R. Rose, "Harmony: Static noise analysis of deep submicron digital integrated circuits," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1132-1150, Aug. 1999.
    • (1999) IEEE Trans. Computer-Aided Design , vol.18 , pp. 1132-1150
    • Shepard, K.L.1    Narayanan, V.2    Rose, R.3
  • 17
  • 19
    • 0024906813 scopus 로고    scopus 로고
    • Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
    • P. R. O'Brien and T. L. Savarino, "Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation," in Proc. Int. Conf. Computer-Aided Design, Nov. 1989, pp. 512-515.
    • Proc. Int. Conf. Computer-Aided Design, Nov. 1989 , pp. 512-515
    • O'Brien, P.R.1    Savarino, T.L.2
  • 20
    • 0028756124 scopus 로고
    • Modeling the effective capacitance for the RC interconnect of CMOS gates
    • Dec.
    • J. Qian, S. Pullela and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1526-1535, Dec. 1994.
    • (1994) IEEE Trans. Computer-Aided Design , vol.13 , pp. 1526-1535
    • Qian, J.1    Pullela, S.2    Pillage, L.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.