New on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

IEEE Transactions on Electron Devices

Volumn 47, Issue 1, 2000, Pages 129-140

  Eo, Yungseon ^a   Eisenstadt, William R ^b   Jeong, Ju Young ^c   Kwon, Oh Kyong ^a  

^a Hanyang University   (South Korea)

^b University of Florida   (United States)

^c Suwon University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC RESISTANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; VLSI CIRCUITS;

DISTRIBUTED PROPERTIES; EFFECTIVE CAPACITANCE; LUMPED MODEL; ON-CHIP INTERCONNECT CROSSTALK MODEL; SIGNAL INTEGRITY;

CROSSTALK;

EID: 0033888853     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.817578     Document Type: Article

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