Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

Integration, the VLSI Journal

Volumn 40, Issue 4, 2007, Pages 394-405

  Kaushik, Brajesh Kumar ^a   Sarkar, Sankar ^a   Agarwal, R P ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

Author keywords

Distributed RLC interconnect; Interconnect modeling; Propagation delay

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; INTERCONNECTION NETWORKS; WAVEFORM ANALYSIS;

DISTRIBUTED RLC INTERCONNECTS; INTERCONNECT MODELING; PROPAGATION DELAYS;

GATES (TRANSISTOR);

EID: 34249001741     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2006.06.001     Document Type: Article

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