Accurate analysis of CMOS inverter driving transmission line based on FDTD

IEEE MTT-S International Microwave Symposium Digest

Volumn , Issue , 2009, Pages 1573-1576

  Li, Xiaochun ^a   Mao, Junfa ^a   Swaminathan, Madhavan ^b  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

CMOS digital integrated circuits; Delay estimation; FDTD methods; Inverters; Time domain analysis; Transmission lines

Indexed keywords

CMOS DIGITAL INTEGRATED CIRCUITS; DELAY ESTIMATION; FDTD METHOD; FDTD METHODS; TRANSMISSION LINE;

BANDPASS FILTERS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC LINES; FINITE DIFFERENCE TIME DOMAIN METHOD; INSULATING MATERIALS; INTEGRATED CIRCUITS; MICROWAVES; MOS DEVICES; TIME DELAY; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; TRANSMISSION LINE THEORY;

CMOS INTEGRATED CIRCUITS;

EID: 77949962148     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSYM.2009.5166011     Document Type: Conference Paper

References (12)

1. T. Sakurai and A. R. Newton, "Alpha-power model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no.2, pp. 584-594, Apr. 1990.
2. D. Auvergne, N. Azemard, and D. Deschacht, "Input waveform slope effects in CMOS delays," IEEE Journal of Solid-State Circuits, vol. 25, no. 6, pp. 1588-1590, Dec. 1990.
3. Santanu Dutta, Shivaling S. Mahant Shetti, and Stephen L. Lusky, "A Comprehensive Delay Model for CMOS Inverters," IEEE Journal of Solid-State Circuits, vol. 30, no.8, pp. 864-871, Aug. 1995.
4. L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, "Analytical Transient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-Channel Devices," IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 302-306, Feb. 1998.
5. A. Chatzigeorgiou, S.Nikolaidis, and I. Tsoukalas, "Modeling CMOS gates driving RC interconnect loads," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no.4, pp. 413-418, Apr. 2001.
6. B. K. Kaushik, S. Sarkara, and R.P. Agarwala, "Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load," Integration, the VLSI journal, vol. 40, pp. 394-405, July 2007.
7. T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE Journal of Solid-State Circuits, vol. 18, no. 4, pp. 418-426, Aug. 1983.
8. J. Rubinstein, P. Penfield, and M.A. Horowitz, "Signal delay in RC tree networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 2, no. 3, pp. 202-211, July 1983.
9. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore delay for RLC trees," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 83-97, Jan. 2000.
10. C. R. Paul, "Incorporation of terminal constraints in the FDTD analysis of transmission lines," IEEE Transactions on Electromagnetic Compatibility, vol. 36, no.2, pp. 85-91, May 1994.
11. X.-C. Li, J.-F. Mao, and H.-F. Huang, "Accurate Analysis of Interconnect Trees With Distributed RLC Model and Moment Matching," IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 9, pp. 2199-2206, Sept. 2004.
12. Xu Q., Li Z. F., Wang J., and Mao J. F., "Transient analysis of lossy interconnects by modified method of characteristics," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 3, pp. 363-375, Mar. 2000.