FDTD modeling of switching noise in multi-layered digital circuits with CMOS inverters and passive lumped elements

IEEE MTT-S International Microwave Symposium Digest

Volumn 3, Issue , 1996, Pages 1787-1790

  Fujii, Masafumi ^a   Murase, Hisanori ^a   Kobayashi, Sumio ^a  

^a Sumitomo Metal Industries   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK ANALYSIS; FINITE DIFFERENCE METHOD; LUMPED PARAMETER NETWORKS; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS;

MULTILAYERED DIGITAL CIRCUITS; PASSIVE LUMPED ELEMENTS; SWITCHING NOISE;

DIGITAL INTEGRATED CIRCUITS;

EID: 0029713474     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)