A new cost-effective metal-insulator-metal capacitor processed at 350 °c Using Ni2Si fully silicided amorphous silicon electrodes

IEEE Transactions on Electron Devices

Volumn 58, Issue 3, 2011, Pages 672-676

  Lee, Jung Hsiang ^a   Lin, Yi Chang ^a   Chen, Bo Han ^a  

^a CHING YUN UNIVERSITY   (Taiwan)

Author keywords

Fully silicided (FUSI); metalinsulatormetal (MIM); Schottky emission; TiO 2

Indexed keywords

FULLY SILICIDED; HIGH-CAPACITANCE DENSITY; INTEGRATION TECHNOLOGIES; MATERIAL CHARACTERIZATIONS; METAL-INSULATOR-METAL CAPACITORS; METALINSULATORMETAL (MIM); MIM CAPACITORS; NEGATIVE FIELDS; NOBLE METALS; POOLE-FRENKEL EFFECT; SCHOTTKY BARRIER HEIGHTS; SCHOTTKY EMISSION; SCHOTTKY EMISSIONS; SILICON ELECTRODE; TIO; TIO 2; TRAP BARRIERS; VOLTAGE COEFFICIENT;

AMORPHOUS SILICON; CAPACITORS; ELECTRODES; METAL INSULATOR BOUNDARIES; PRECIOUS METALS; SCHOTTKY BARRIER DIODES; SILICIDES;

MIM DEVICES;

EID: 79952041218     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2103561     Document Type: Article

References (34)

1. J. H. Klootwijk, K. B. Jinesh, W. Dekkers, J. F. Verhoeven, F. C. van den Heuvel, H. D. Kim, D. Blin, M. A. Verheijen, R. G. R. Weemaes, M. Kaiser, J. J. M. Ruigrok, and F. Roozeboom, "Ultrahigh capacitance density for multiple ALD-grown MIM capacitor stacks in 3-D silicon," IEEE Electron Device Lett., vol. 29, no. 7, pp. 740-742, Jul. 2008.
2. M. Danek, M. Liao, J. Tseng, K. Littau, D. Saigal, H. Zhang, R. Mosely, and M. Eizenberg, "Resistivity reduction and chemical stabilization of organometallic chemical vapor deposited titanium nitride by nitrogen rf plasma," Appl. Phys. Lett., vol. 68, no. 7, pp. 1015-1016, Feb. 1996. (Pubitemid 126684487)
3. C. S. Kang, H. J. Cho, Y. H. Kim, R. Choi, K. Onishi, A. Shahriar, and J. C. Lee, "Characterization of resistivity and work function of sputtered-TaN film for gate electrode applications," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 21, no. 5, pp. 2026-2028, Sep. 2003.
4. C. Ren, D. S. H. Chan, M. F. Li, W. Y. Loh, S. Balakumar, C. H. Tung, N. Balasubramanian, and D. L. Kwong, "Work function tuning and material characteristics of lanthanide-incorporated metal nitride gate electrodes for NMOS device applications," IEEE Trans. Electron Devices, vol. 53, no. 8, pp. 1877-1884, Aug. 2006. (Pubitemid 44145094)
5. T. Kim, J. N. Hanson, A. Gruverman, A. I. Kingon, and S. K. Streiffer, "Ferroelectric behavior in nominally relaxor lead lanthanum zirconate titanate thin films prepared by chemical solution deposition on copper foil," Appl. Phys. Lett., vol. 88, no. 26, p. 262 907, Jun. 2006.
6. S.M. Aygün, "Hot sputtering of barium strontium titanate on nickel foils," J. Appl. Phys., vol. 103, no. 8, p. 084 123, Apr. 2008.
7. 5 capacitor with enhanced dielectric constant for DRAMs of G-bit generation and beyond," in VLSI Symp. Tech. Dig., 2001, pp. 41-42. (Pubitemid 32950651)
8. 5/CVD-TiN capacitor for multigigabit-scale DRAM generation," in VLSI Symp. Tech. Dig., 2000, pp. 100-101.
9. K. Fröhlich, K. Husekova, D. Machajdik, J. C. Hooker, N. Perez, M. Fanciulli, S. Ferrari, C. Wiemer, A. Dimoulas, G. Vellianitis, and F. Roozeboom, "Ru and RuO2 gate electrodes for advanced CMOS technology," Mater. Sci. Eng. B, vol. 109, no. 1-3, pp. 117-121, Jun. 2004.
10. J. J. Yang, X. P. Wang, C. X. Zhu, M. F. Li, H. Y. Yu, W. Y. Loh, and D. L. Kwong, "Enhancement of the flatband modulation of Ni-silicided gates on Hf-based dielectrics," IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 2238-2245, Aug. 2008.
11. T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, H. Tigelaar, M. Van Dal, T. Chiarella, C. Kerner, T. Kauerauf, A. Shickova, R. Mitsuhashi, I. Satoru, M. Niwa, A. Rothschild, B. Froment, J. Ramos, A. Nackaerts, M. Rosmeulen, S. Brus, C. Vrancken, P. P. Absil, M. Jurczak, S. Biesemans, and J. A. Kittl, "Ni-based FUSI gates: CMOS integration for 45 nm node and beyond," in IEDM Tech. Dig., 2006, pp. 1-4.
12. Y. Shacham-Diamand, T. Osaka, M. Datta, and T. Ohba, Advanced Nanoscale ULSI Interconnects: Fundamentals and Applications. New York: Springer-Verlag, 2009, pt. 6, p. 275.
13. P. Zhao, M. J. Kim, B. E. Gnade, and R. M. Wallace, "Thermal stability studies of fully silicided NiSi on Si-oxynitride and Hf-based high-k gate stacks," J. Appl. Phys., vol. 101, no. 5, p. 053 504, Mar. 2007.
14. 3 gate dielectrics," in VLSI Symp. Tech. Dig., 2003, pp. 119-120.
15. 3-Ge-on-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates," IEEE Electron Device Lett., vol. 25, no. 3, pp. 138-140, Mar. 2004.
16. C. C. Liao, S. Kao, A. Chin, D. S. Yu, M.-F. Li, C. Zhu, and S. P. McAlister, "Comparing high mobility InGaAs FETs with Si and GOI devices," in Proc. 64th Device Res. Conf., 2006, pp. 85-86.
17. J.-H. Lee, Z.-Y. Tsai, Y.-C. Lin, Y.-Y. Zhu, and B.-H. Chen, "A new metalinsulator- metal capacitor with nickel fully silicided polycrystalline silicon electrodes," Jpn. J. Appl. Phys., vol. 49, no. 9, p. 091 503, Sep. 2010.
18. M. Tinani, A. Mueller, Y. Gao, E. A. Irene, Y. Z. Hu, and S. P. Tay, "In situ real-time studies of nickel silicide phase formation," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 19, no. 2, pp. 376-383, Mar. 2001. (Pubitemid 32435258)
19. C. Lavoie, R. Purtell, C. Coiumla, C. Detavernier, P. Desjardins, J. Jordan-Sweet, C. Cabral, Jr., F. M. d'Heurle, and J. M. E. Harper, "In situ monitoring of thin film reactions during rapid thermal annealing: Nickel silicide formation," in Proc. Electrochem. Soc., 2002, vol. PV 2002-11, pp. 455-468.
20. T. Murakami1, B. Froment, V. Carron, M. Ouaknine, and W. S. Yoo, "Nickel silicide formation using a stacked hotplate-based low temperature annealing system," presented at the 203rd Electrochemical Society Meeting, Paris, France, 2003.
21. F. Deng, R. A. Johnson, P. M. Asbeck, S. S. Lau, W. B. Dubbelday, T. Hsiao, and J. Woo, "Salicidation process using NiSi and its device application," J. Appl. Phys., vol. 81, no. 12, p. 8047, Jun. 1997.
22. 2Si thin films," Microelectron. Eng., vol. 87, no. 3, pp. 263-266, Mar. 2010.
23. 2O annealing," in IEDM Tech. Dig., 1994, pp. 333-336.
24. K. S. Tan, S. Kiriaki, M. D. Wit, J. W. Fattaruso, C. Y. Tsay, W. E. Matthews, and R. K. Hester, "Error correction techniques for high-performance differential A/D converters," IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1318-1327, Dec. 1990. (Pubitemid 21738095)
25. 3/TaN capacitors for analog and RF applications," in VLSI Symp. Tech. Dig., 2006, pp. 102-103. (Pubitemid 351424146)
26. T. Hori, Gate Dielectrics and MOS ULSIs. New York: Springer-Verlag, 1997, pp. 44-57.
27. 2 films," Appl. Phys. Lett., vol. 79, no. 17, pp. 2803-2804, Oct. 2001. (Pubitemid 33664697)
28. 2 high-κ gate dielectric stack on 4H-SiC substrate," J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 25, no. 1, pp. 217-223, Jan. 2007. (Pubitemid 46512030)
29. 3Si fully silicided gates," IEEE Electron Device Lett., vol. 27, no. 1, pp. 34-36, Jan. 2006.
30. 2/Si structure," J. Appl. Phys., vol. 97, no. 3, p. 034 506, Feb. 2005.
31. 2/Si structures," Eur. Phys. J. B, vol. 52, no. 4, pp. 453-457, Aug. 2006.
32. 2 thin films deposited by a DC magnetron sputtering system," Thin Solid Films, vol. 372, no. 1/2, pp. 246-249, Sep. 2000.
33. 2 films containing anatase and rutile," J. Semicond. Sci. Technol., vol. 20, no. 8, pp. 870-875, Aug. 2005. (Pubitemid 41036989)
34. M. C. Poon, F. Deng, M. Chan, W. Y. Chan, and S. S. Lau, "Resistivity and thermal stability of nickel mono-silicide," Appl. Surf. Sci., vol. 157, no. 1/2, pp. 29-34, Mar. 2000. (Pubitemid 30565699)