A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

Microprocessors and Microsystems

Volumn 35, Issue 2, 2011, Pages 139-151

  Jackson, Chris ^a   Hollis, Simon J ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

Deadlock; NoCs; Reconfigurable; Routing; Topology

Indexed keywords

DEADLOCK; DEADLOCK-FREE ROUTING; DYNAMIC TOPOLOGIES; DYNAMICALLY RECONFIGURABLE NETWORK; ENERGY COST; HOP COUNT; INPUT BUFFERS; IRREGULAR MESHES; IRREGULAR TOPOLOGY; LINK STRUCTURE; LOCAL TOPOLOGY; LONG-RANGE LINKS; MINIMAL PATH; NETWORKS ON CHIPS; NOCS; OPTIMAL PATHS; OUTPUT PORTS; RE-CONFIGURABLE; REGULAR MESHES; ROUTABILITY; ROUTING; ROUTING DECISIONS; RUNTIMES; SELECTION FUNCTION; STANDARD ALGORITHMS; TWO STAGE;

MESH NETWORKING; ROUTING ALGORITHMS;

TOPOLOGY;

EID: 79951869402     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2010.09.004     Document Type: Article

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