Router designs for elastic buffer on-chip networks

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC '09

Volumn , Issue , 2009, Pages

  Michelogiannakis, George ^a   Dally, William J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

On chip networks

Indexed keywords

CLOCK FREQUENCY; CYCLE TIME; DESIGN SPACES; ELASTIC BUFFER; LOOK-AHEAD; ON-CHIP NETWORKS; ROUTER DESIGN; SINGLE STAGE; TWO STAGE;

DESIGN; ELECTRIC NETWORK TOPOLOGY;

ROUTERS;

EID: 74049134328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1654059.1654062     Document Type: Conference Paper

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