A high-throughput distributed shared-buffer NoC router

IEEE Computer Architecture Letters

Volumn 8, Issue 1, 2009, Pages 21-24

  Soteriou, Vassos ^a   Ramanujam, Rohit Sunkam ^b   Lin, Bill ^b   Peh, Li Shiuan ^c  

^a CYPRUS UNIVERSITY OF TECHNOLOGY   (Cyprus)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH LOAD; HIGH-THROUGHPUT; MICRO ARCHITECTURES; ON-CHIP NETWORKS; POWER BUDGETS; QUEUING DELAY; ROUTER ARCHITECTURE; ROUTER DESIGN; SATURATION THROUGHPUT; SIGNIFICANT IMPACTS;

COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; NETWORK ARCHITECTURE; VIDEO AMPLIFIERS;

ROUTERS;

EID: 67650581749     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2009.5     Document Type: Article

References (16)

1. Shang-Tse Chuang, A. Goel, N. McKeown, and B. Prabhakar. Matching output queueing with a combined input/output-queued switch. IEEE Journal on Selected Areas in Communications, Jun 1999.
2. W. J. Dally. Virtual-channel flow control. In ISCA, May 1990.
3. P. Gratz et al. Implementation and evaluation of on-chip network architectures. In ICCD, Oct. 2006.
4. S. Iyer, R. Zhang, and N. McKeown. Routers with a single stage of buffering. In ACM SIGCOMM, September 2002.
5. Jongman Kim, C. Nicopoulos, and Dongkook Park. A gracefully degrading and energy-efficient modular router architecture for on-chip networks. ISCA, pages 4-15, 2006.
6. A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. Express virtual channels: Towards the ideal interconnection fabric. In ISCA, June 2007.
7. A. Kumar et al. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. In ICCD, Oct. 2007.
8. S. S. Mukherjee et al. The Alpha 21364 network architecture. IEEE Micro, 22(1):26-35, Jan./Feb. 2002.
9. R. Mullins et al. Low-latency virtual-channel routers for on-chip networks. In ISCA, June 2004.
10. C. A. Nicopoulos et al. ViChaR: A dynamic virtual channel regulator for network-on-chip routers. In MICRO, Dec. 2006.
11. Li-Shiuan Peh and William J. Dally. A delay model and speculative architecture for pipelined routers. In HPCA, Jan. 2001.
12. Li-Shiuan Peh and W.J. Dally. Flit-reservation flow control. HPCA, pages 73-84, 2000.
13. A. Prakash, A. Aziz, and V. Ramachandran. Randomized parallel schedulers for switch-memory-switch routers: Analysis and numerical studies. In IEEE INFOCOM, March 2004.
14. S. Vangal et al. An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In ISSCC, Feb. 2007.
15. H.-S. Wang et al. Orion: A power-performance simulator for interconnection networks. In MICRO, Nov. 2002.
16. H.-S. Wang et al. Power-driven design of router microarchitectures in on-chip networks. In MICRO, Nov. 2003.