Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs

2010 International Symposium on System-on-Chip Proceedings, SoC 2010

Volumn , Issue , 2010, Pages 49-54

  Jackson, Chris ^a   Hollis, Simon J ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLE-ACCURATE SIMULATION; ENERGY EFFICIENT; ENERGY REDUCTION; EXISTING METHOD; HOP COUNT; LONG-RANGE LINKS; MANY-CORE; MESH ARCHITECTURE; MESH TOPOLOGIES; NETWORK ON CHIP; PROPOSED ARCHITECTURES; RE-CONFIGURABLE; RUNTIMES; SWITCHING ACTIVITIES; TRAFFIC PATTERN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BEHAVIORAL RESEARCH; PROGRAMMABLE LOGIC CONTROLLERS; ROUTERS; TOPOLOGY; VLSI CIRCUITS;

NETWORK ARCHITECTURE;

EID: 78650204031     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2010.5625537     Document Type: Conference Paper

References (20)

1. W. J. Dally and B. Towles, "Route packets, not wires: on-chip inteconnection networks," in DAC '01: Proc. of the 38th conference on Design automation. New York, NY, USA: ACM, 2001, pp. 684-689.
2. A. Banerjee, R. Mullins, and S. Moore, "A power and energy exploration of network-on-chip architectures," Networks-on-Chip, 2007. NOCS 2007. First International Symposium on, pp. 163-172, May 2007.
3. G. Michelogiannakis and W. J. Dally, "Router designs for elastic buffer on-chip networks," in SC '09: Proc. of the Conference on High Performance Computing Networking, Storage and Analysis. New York, NY, USA: ACM, 2009, pp. 1-10.
4. L. Schwiebert and D. N. Jayasimha, "Optimal fully adaptive wormhole routing for meshes," in Supercomputing '93: Proc. of the 1993 ACM/IEEE conference on Supercomputing. New York, NY, USA: ACM, 1993, pp. 782-791.
5. B. Towles, W. J. Dally, and S. Boyd, "Throughput-centric routing algorithm design," in SPAA '03: Proc. of the fifteenth annual ACM symposium on Parallel algorithms and architectures. New York, NY, USA: ACM, 2003, pp. 200-209.
6. K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, P. Husbands, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, and K. A. Yelick, "The landscape of parallel computing research: A view from berkeley," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2006-183, Dec 2006.
7. J. Shalf, S. Kamil, L. Oliker, and D. Skinner, "Analyzing ultra-scale application communication requirements for a reconfigurable hybrid interconnect," in SC '05: Proc. of the 2005 ACM/IEEE conference on Supercomputing. Washington, DC, USA: IEEE Computer Society, 2005, p. 17.
8. S. Moore and D. Greenfield, "The next resource war: computation vs. communication," in SLIP '08: Proc. of the 2008 international workshop on System level interconnect prediction. New York, NY, USA: ACM, 2008, pp. 81-86.
9. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular noc architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, April 2005.
10. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," Design Automation Conference, 2002. Proc.. 39th, pp. 524-529, 2002.
11. R. Mullins, "Minimising dynamic power consumption in on-chip networks," System-on-Chip, 2006. International Symposium on, pp. 1-4, Nov. 2006.
12. V. Soteriou and L.-S. Peh, "Design-space exploration of power-aware on/off interconnection networks," in Proc. of the 22nd International Conference on Computer Design (ICCD), October 2004.
13. K. Lee, S. Member, S. joong Lee, H. jun Yoo, and S. Member, "Low-power network-on-chip for high-performance soc design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 148-160, 2006.
14. V. Nollet, T. Marescaux, D. Verkest, J.-Y. Mignolet, and S. Vernalde, "Operating-system controlled network on chip," in DAC '04: Proc. of the 41st annual conference on Design automation. New York, NY, USA: ACM, 2004, pp. 256-259.
15. G. Chen, F. Li, and M. Kandemir, "Compiler-directed application mapping for noc based chip multiprocessors," SIGPLAN Not., vol. 42, no. 7, pp. 155-157, 2007.
16. S. J. Hollis and C. Jackson, "When does network-on-chip bypassing make sense?" in 22nd IEEE SoCC Conference. IEEE Circuits and Systems Society, 2009.
17. M. B. Stensgaard and J. Sparsø, "Renoc: A network-on-chip architecture with reconfigurable topology," in NOCS '08: Proc. of the Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008). Washington, DC, USA: IEEE Computer Society, 2008, pp. 55-64.
18. A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha, "Express virtual channels: towards the ideal interconnection fabric," SIGARCH Comput. Archit. News, vol. 35, no. 2, pp. 150-161, 2007.
19. U. Y. Ogras and R. Marculescu, "Its a small world after all': Noc performance optimization via long-range link insertion," IEEE Trans. on Very Large Scale Integration Systems, Special Section on Hardware/Software Codesign and System Synthesis, vol. 14, no. 7, pp. 693-706, July 2006.
20. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco, CA, USA: Morgan Kaufmann, 2003.