FPGA-array with bandwidth-reduction mechanism for scalable and power-efficient numerical simulations based on finite difference methods

ACM Transactions on Reconfigurable Technology and Systems

Volumn 3, Issue 4, 2010, Pages

  Sano, Kentaro ^a   Luzhou, Wang ^a   Hatsuda, Yoshiaki ^a   Iizuka, Takanori ^a   Yamamoto, Satoru ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Finite difference methods; FPGAs; Reconfigurable computing; Scalable array

Indexed keywords

2D ARRAYS; ARITHMETIC PERFORMANCE; ARRAY SIZES; BANDWIDTH REQUIREMENT; BANDWIDTH-AWARE; COMPUTING UNITS; DATA ACCESS; DELAY CYCLE; HIGH PRODUCTIVITY; I/O BANDWIDTH; MEMORY BANDWIDTHS; MESH NETWORK; PEAK PERFORMANCE; PERFORMANCE IMPROVEMENTS; POWER EFFICIENT; PROCESSING ELEMENTS; PROGRAMMABILITY; RECONFIGURABLE COMPUTING; SCALABLE ARRAY; SCIENTIFIC SIMULATIONS; SINGLE PRECISION; SOFTWARE SIMULATION; SUSTAINED PERFORMANCE;

BANDWIDTH; COMMUNICATION; COMPUTER SIMULATION; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FINITE DIFFERENCE METHOD; MEMORY ARCHITECTURE; RECONFIGURABLE ARCHITECTURES; SCALABILITY;

TELECOMMUNICATION SYSTEMS;

EID: 79551552121     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1862648.1862651     Document Type: Article

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