Systolic architecture for computational fluid dynamics on FPGAs

Proceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Volumn , Issue , 2007, Pages 107-116

  Sano, Kentaro ^a   Iizuka, Takanori ^a   Yamamoto, Satoru ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL FLUID DYNAMICS; COMPUTERS; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLOW SIMULATION;

CENTRAL DIFFERENCE SCHEME; DEDICATED PROCESSORS; DRIVEN CAVITY FLOW; FRACTIONAL STEP METHODS; LOCAL MEMORY; PEAK PERFORMANCE; SINGLE PRECISION; SYSTOLIC ARCHITECTURE;

SYSTOLIC ARRAYS;

EID: 47349089632     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2007.20     Document Type: Conference Paper

References (20)

1. M. deLorimier and A. DeHon. Floating-point sparse matrix-vector multiply for fpgas. Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 75-85, February 2005.
2. Y. Dou, S. Vassiliadis, G. K. Kuzmanov, and G. N. Gaydadjiev. 64-bit floating-point fpga matrix multiplication. Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 86-95, February 2005.
3. J. P. Durbano, F. E. Ortiz, J. R. Humphrey, P. F. Curt, and D. W. Prather. Fpga-based acceleration of the 3d finite-difference time-domain method. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 156-163, April 2004.
4. D. G. Elliott, M. Stumm, W. Snelgrove, C. Cojocaru, and R. Mckenzie. Computational ram: Implementing processors in memory. Design & Test of Computers, 16(1):32-41, January-March 1999.
5. J. H. Ferziger and M. Perić. Computational Methods for Fluid Dynamics. Springer-Verlag Berlin Heidelberg, 1996.
6. T. Hauser. A flow solver for a reconfigurable fpga-based hypercomputer. AIAA Aerospace Sciences Meeting and Exhibit, 2005.
7. C. He, M. Lu, and C. Sun. Accelerating seismic migration using fpga-based coprocessor platform. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 207-216, April 2004.
8. C. He,W. Zhao, and M. Lu. Time domain numerical simulation for transient waves on reconfigurable coprocessor platform. Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 127-136, April 2005.
9. J. Kim and P.Moin. Application of a fractional-step method to incompressible navier-stokes. Journal of Computational Physics, 59:308-323, June 1985.
10. H. T. Kung. Why systolic architecture? Computer, 15(1):37-46, 1982.
11. D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick. A case for intelligent ram: Iram. IEEE Micro, 17(2):34-44, March/April 1997.
12. D. Patterson, K. Asanovic, A. Brown, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, C. Kozyrakis, D. Martin, S. Perissakis, R. Thomas, N. Treuhaft, and K. Yelick. Intelligent ram(iram): the industrial setting, applications, and architectures. Proceedings of the International Conference on Computer Design, pages 2-9, October 1997.
13. K. Sano, C. Takagi, R. Egawa, K. Suzuki, and T. Nakamura. A systolic memory architecture for fast codebook design based on mmpdcl algorithm. Proceedings of the International Conference on Information Technology(ITCC2004), pages 572-578, April 2004.
14. K. Sano, C. Takagi, and T. Nakamura. Systolic computational memory approach to high-speed codebook design. Proceedings of the 5th IEEE International Symposium on Signal Processing and Information Technology (ISSPIT2005), pages 334-339, December 2005.
15. R. Scrofano, M. Gokhale, F. Trouw, and V. K. Prasanna. A hardware/software approach to molecular dynamics on reconfigurable computers. Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 23-34, April 2006.
16. N. Shirazi, A.Walters, and P. Athanas. Quantitative analysis of floating point arithmetic on fpga based custom computing machines. Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, pages 155-162, 1995.
17. J. C. Strikwerda and Y. S. Lee. The accuracy of the fractional step method. SIAM Journal on Numerical Analysis, 37(1):37-47, November 1999.
18. K. Underwood. Fpga vs. cpus: Trends in peak floatingpoint performance. Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 171-180, February 2004.
19. K. D. Underwood and K. S. Hemmert. Closing the gap: Cpu and fpga trends in sustainable floating-point blas performance. Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 219-228, 2004.
20. L. Zhuo and V. K. Prasanna. Sparse matrix-vector multiplication on fpgas. Proceedings of the International Symposium on Field-Programmable Gate Arrays, pages 63-74, February 2005.