Systolic computational memory approach to high-speed codebook design

Proceedings of the Fifth IEEE International Symposium on Signal Processing and Information Technology

Volumn 2005, Issue , 2005, Pages 334-339

  Sano, Kentaro ^a   Takagi, Chiaki ^b   Nakamura, Tadao ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NHK SCIENCE AND TECHNICAL RESEARCH LABORATORIES   (Japan)

Author keywords

Codebook design; Computational memory; MMPDCL algorithm; Systolic architecture; Vector quantization

Indexed keywords

BANDWIDTH; CODES (SYMBOLS); COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RANDOM ACCESS STORAGE; SOFTWARE PROTOTYPING; VECTOR QUANTIZATION;

CODEBOOK DESIGNS; MINI MAX PARTIAL DISTORTION COMPETITIVE LEARNING (MMPDCL) ALGORITHM; SYSTOLIC ARCHITECTURE; SYSTOLIC COMPUTATIONAL MEMORY;

SYSTOLIC ARRAYS;

EID: 33846975089     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSPIT.2005.1577119     Document Type: Conference Paper

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