A systolic memory architecture for fast codebook design based on MMPDCL algorithm

International Conference on Information Technology: Coding Computing, ITCC

Volumn 1, Issue , 2004, Pages 572-578

  Sano, Kentaro ^a   Takagi, Chiaki ^a   Egawa, Ryusuke ^a   Suzuki, Kenichi ^a   Nakamura, Tadao ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Codebook design; MMPDCL algorithm; Systolic memory architecture; Vector quantization

Indexed keywords

CODEBOOK DESIGN; MMPDCL ALGORITHMS; SCALAR QUANTIZATION; SYSTOLIC MEMORY ARCHITECTURE;

CODES (SYMBOLS); COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ERROR DETECTION; LEARNING ALGORITHMS; PROGRAM PROCESSORS; REAL TIME SYSTEMS; VECTOR QUANTIZATION;

COMPUTER ARCHITECTURE;

EID: 3042542332     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITCC.2004.1286525     Document Type: Conference Paper

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