High-performance reduction circuits using deeply pipelined operators on FPGAs

IEEE Transactions on Parallel and Distributed Systems

Volumn 18, Issue 10, 2007, Pages 1377-1392

  Zhou, Ling ^a   Morris, Gerald R ^b   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

^b CEERD IH   (United States)

Author keywords

Parallel algorithms; Reconfigurable hardware

Indexed keywords

COMPUTER HARDWARE; NETWORKS (CIRCUITS); PARALLEL ALGORITHMS; SEQUENTIAL CIRCUITS;

RECONFIGURABLE HARDWARE; STRIDING METHOD; TREE-TRAVERSAL METHOD;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34648814129     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2007.1068     Document Type: Article

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