A scalable FPGA-based multiprocessor

Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006

Volumn , Issue , 2006, Pages 111-120

  Patel, Arun ^a   Madill, Christopher A ^a,b   Saldaña, Manuel ^a   Comis, Christopher ^a,c   Pomès, Régis ^a,b   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b HOSPITAL FOR SICK CHILDREN   (Canada)

^c PMC Sierra Ltd Burnaby   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE ACCELERATORS; MOLECULAR DYNAMICS SIMULATIONS; TIME SCALES;

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LARGE SCALE SYSTEMS; THROUGHPUT;

MULTIPROCESSING SYSTEMS;

EID: 34547427510     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.17     Document Type: Conference Paper

References (36)

1. V. Aggarwal, I. A. Troxel, and A. D. George. Design and Analysis of Parallel N-Queens on Reconfigurable Hardware with Handel-C and MPI. In 2004 MAPLD International Conference, Washington, DC, USA, 2004.
2. M. P. Alien and D. J. Tildesley. Computer simulation of liquids. Clarendon Press, New York, NY, USA, 1987.
3. Altera, the Leader in Programmable Logic. http://www.altera.com/. Curr. Jan. 2006.
4. AP1000 PCI Platform FPGA Development Board. Technical report, Amirix Systems, Inc., Oct. 2005. http://www.amirix.com/downloads/ap1000.pdf.
5. D. Brady. FPGA I/O Features Help Lower Overall PCS Costs. FPGA and Structured ASIC Journal, Aug. 2004. http://www.fpgajournal.com/articles/ 20040810_mentor.htm.
6. G. Burns, R. Daoud, and J. Vaigl. LAM: An Open Cluster Environment for MPI. In Proceedings of Supercomputing Symposium, pages 379-386, 1994.
7. D. Case, I. T.E. Cheatham, T. Darden, H. Gohlke, R. Luo, K. M. Jr., A. Onufriev, C. Simmerling, B. Wang, and R. Woods. The Amber biomolecular simulation programs. In Proceedings of JCCM '05, volume 26, pages 1668-1688, 2005.
8. C. Chang, K. Kuusilinna, B. Richards, A. Chen, N. Chan, R. W. Brodersen, and B. Nikolic. Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment. In Proceedings of RSP '03, pages 148-, 2003.
9. C. Chang, J. Wawrzynek, and R. W. Brodersen. BEE2: A High-End Reconfigurable Computing System. IEEE Des. Test '05, 22(2):114-125, 2005.
10. C. J. Comis. A High-speed Inter-process Communication Architecture for FPGA-based Hardware Acceleration of Molecular Dynamics. Master's thesis, University of Toronto, 2005.
11. Cray XD1 supercomputer for reconfigurable computing. Technical report, Cray, Inc., 2005. http: //www.cray.com/downloads/FPGADatasheet.pdf.
12. FPGA High Performance Computing Alliance. http://www.fhpca.org/. Curr. Jan. 2006.
13. R. S. Germain, B. Fitch, A. Rayshubskiy, M. Eleftheriou, M. C. Pitman, F. Suits, M. Giampapa, and T. C. Ward. Blue matter on blue gene/1: massively parallel computation for biomolecular simulation. In Proceedings of CODES+ISSS '05, pages 207-212, New York, NY, USA, 2005. ACM Press.
14. R. L. Graham, T. S. Woodall, and J. M. Squyres Open MPI: A flexible high performance MPI. In Proceedings of PPAM '05, Poznan, Poland, Sept. 2005.
15. W. Gropp, E. Lusk, N. Doss, and A. Skjellum. A high-performance, portable implementation of the MPI message passing interface standard. Parallel Computing, 22(6):789-828, Sept. 1996.
16. T. Hamada, T. Fukushige, A. Kawai, and J. Makino. PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body Simulations. In FCCM, pages 256-257, 1998.
17. Handel-C Documentation, http://www.celoxica.com. Curr. Jan. 2006.
18. Y.-S. Hwang, R. Das, J. H. Saltz, M. Hodoscek, and B. R. Brooks. Parallelizing molecular dynamics programs for distributed-memory machines. IEEE Computational Science & Engineering, 2(2):18-29, Summer 1995.
19. IEEE802.3 10GBASE-CX4 Study Group. http://www.ieee802.Org/3/10GBCX4/, Mar. 2002. Curr. Jan. 2006.
20. The InflniBand Architecture Specification R1.2. Technical report, InfiniBand Trade Association, Oct. 2004. http://www.infinibandta.org.
21. D. Ku and G. DeMicheli. HardwareC - A language for hardware design. Technical Report CSL-TR-90-419, Stanford University, 1988.
22. T. P. McMahon and A. Skjellum. eMPI/eMPICH: Embedding MPI. In Proceedings of MPIDC '96, page 180, Washington, DC, USA, 1996. IEEE Computer Society.
23. MPI - Message Passing Interface. http://www-unix.mcs.anl.gov/mpi/. Curr. Jan. 2006.
24. OpenFPGA - Denning Reconflgurable Supercomputing. http://www.openfpga. org/. Curr. Jan. 2006.
25. J. C. Phillips, R. Braun, W. Wang, J. Gumbart, E. Tajkhorshid, E. Villa, C. Chipot, R. D. Skeel, L. Kale, and K. Schulten. Scalable molecular dynamics with NAMD. In Proceedings of JCCM '05, volume 26, pages 1781-1802, 2005.
26. J. C. Phillips, G. Zheng, S. Kumar, and L. V. Kale. NAMD: biomolecular simulation on thousands of processors. In Proceedings of Supercomputing '02, pages 1-18, Los Alamitos, CA, USA, 2002. IEEE Computer Society Press.
27. M. Saldaña, L. Shannon, and P. Chow. The Rout ability of Multiprocessor Network Topologies in FPGAs. In Proceedings of SLIP '06, 2006. (To Appear in March).
28. Extraordinary Acceleration of Workflows with Reconflgurable Application-specific Computing from SGI. Technical report, Silicon Graphics, Inc., Nov. 2004. http://www.sgi.com/pdfs/3721.pdf.
29. The MathWorks - MATLAB and Simulink for Technical Computing, http://www.mathworks.com/. Curr. Jan. 2006.
30. D. Soderman and Y. Panchul. Implementing c algorithms in reconfigurable hardware using c2verilog. In Proceedings of FCCM '98, page 339, Washington, DC, USA, 1998. IEEE Computer Society.
31. General Purpose Reconfigurable Computing Systems. 2005. SRC Computers, Inc. http://www.srccomp.com/.
32. M. Taiji, T. Narumi, Y. Ohno, and A. Konagaya. MDGRAPE-3: A Petaflops Special-Purpose Computer System for Molecular Dynamics Simulations. In Proceedings of PARCO '05, pages 669-676, 2003.
33. uClinux Embedded Linux/Microcontroller Project. http://www.uclinux.org/. Curr. Jan. 2006.
34. K. D. Underwood, K. S. Hemmert, A. Rodrigues, R. Murphy, and R. Brightwell. A Hardware Acceleration Unit for MPI Queue Processing. In Proceedings of IPDPS '05, page 96.2, Washington, DC, USA, 2005. IEEE Computer Society.
35. Xilinx - The Programmable Logic Company. http://www.xilinx.com/. Curr. Jan. 2006.
36. M.-W. Youssef, S. Yoo, A. Sasongko, Y. Paviot, and A. A. Jerraya. Debugging HW/SW interface for MPSoC: video encoder system design case study. In Proceedings of DAC '04, pages 908-913, New York, NY, USA, 2004. ACM Press.