Quality of Service shared cache management in chip multiprocessor architecture

Transactions on Architecture and Code Optimization

Volumn 7, Issue 3, 2010, Pages

  Guo, Fei ^a   Solihin, Yan ^b   Zhao, Li ^c   Iyer, Ravishankar ^c  

^a VMWARE INC   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Cache; Chip multi processors; CMP; Multicore architecture; Performance; QoS; Quality of Service; Resource stealing

Indexed keywords

CACHE; CHIP MULTI-PROCESSORS; CMP; MULTICORE ARCHITECTURE; PERFORMANCE; QOS; RESOURCE STEALING;

COMPUTER OPERATING SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY CONTROL; SOFTWARE ARCHITECTURE; SYSTEMS ANALYSIS; TELECOMMUNICATION SERVICES; THROUGHPUT;

QUALITY OF SERVICE;

EID: 78651391009     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1880037.1880039     Document Type: Article

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